Source-Changes-HG archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

[src/trunk]: src/sys/arch/arm/allwinner work in progress CIR driver



details:   https://anonhg.NetBSD.org/src/rev/9f52c2107b77
branches:  trunk
changeset: 333422:9f52c2107b77
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Nov 02 23:55:48 2014 +0000

description:
work in progress CIR driver

diffstat:

 sys/arch/arm/allwinner/awin_io.c  |    5 +-
 sys/arch/arm/allwinner/awin_ir.c  |  314 ++++++++++++++++++++++++++++++++++++++
 sys/arch/arm/allwinner/files.awin |    7 +-
 3 files changed, 324 insertions(+), 2 deletions(-)

diffs (truncated from 358 to 300 lines):

diff -r 1d77cde4b4c3 -r 9f52c2107b77 sys/arch/arm/allwinner/awin_io.c
--- a/sys/arch/arm/allwinner/awin_io.c  Sun Nov 02 23:55:06 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_io.c  Sun Nov 02 23:55:48 2014 +0000
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.23 2014/10/19 23:18:22 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_io.c,v 1.24 2014/11/02 23:55:48 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -147,6 +147,9 @@
        { "awincrypto", OFFANDSIZE(SS), NOPORT, AWIN_IRQ_SS, AANY },
        { "awinac", OFFANDSIZE(AC), NOPORT, AWIN_IRQ_AC, A10|A20 },
        { "awinac", OFFANDSIZE(AC), NOPORT, AWIN_A31_IRQ_AC, A31 },
+       { "awinir", OFFANDSIZE(IR0), 0, AWIN_IRQ_IR0, A10|A20 },
+       { "awinir", OFFANDSIZE(IR1), 1, AWIN_IRQ_IR1, A10|A20 },
+       { "awinir", OFFANDSIZE(A31_CIR), NOPORT, AWIN_A31_IRQ_CIR, A31 },
 };
 
 static int
diff -r 1d77cde4b4c3 -r 9f52c2107b77 sys/arch/arm/allwinner/awin_ir.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/allwinner/awin_ir.c  Sun Nov 02 23:55:48 2014 +0000
@@ -0,0 +1,314 @@
+/* $NetBSD: awin_ir.c,v 1.1 2014/11/02 23:55:48 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_ddb.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: awin_ir.c,v 1.1 2014/11/02 23:55:48 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/select.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+
+#include <arm/allwinner/awin_reg.h>
+#include <arm/allwinner/awin_var.h>
+
+#include <dev/ir/ir.h>
+#include <dev/ir/cirio.h>
+#include <dev/ir/cirvar.h>
+
+#define AWIN_IR_RXSTA_MASK     __BITS(7,0)
+
+struct awin_ir_softc {
+       device_t sc_dev;
+       device_t sc_cirdev;
+       bus_space_tag_t sc_bst;
+       bus_space_handle_t sc_bsh;
+       kmutex_t sc_lock;
+       kcondvar_t sc_cv;
+       device_t sc_i2cdev;
+       void *sc_ih;
+       size_t sc_avail;
+};
+
+#define IR_READ(sc, reg) \
+    bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define IR_WRITE(sc, reg, val) \
+    bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static int     awin_ir_match(device_t, cfdata_t, void *);
+static void    awin_ir_attach(device_t, device_t, void *);
+
+static void    awin_ir_init(struct awin_ir_softc *,
+                            struct awinio_attach_args * const);
+
+static int     awin_ir_intr(void *);
+
+static int     awin_ir_open(void *, int, int, struct proc *);
+static int     awin_ir_close(void *, int, int, struct proc *);
+static int     awin_ir_read(void *, struct uio *, int);
+static int     awin_ir_write(void *, struct uio *, int);
+static int     awin_ir_setparams(void *, struct cir_params *);
+
+#ifdef DDB
+void           awin_ir_dump_regs(void);
+#endif
+
+static const struct cir_methods awin_ir_methods = {
+       .im_open = awin_ir_open,
+       .im_close = awin_ir_close,
+       .im_read = awin_ir_read,
+       .im_write = awin_ir_write,
+       .im_setparams = awin_ir_setparams,
+};
+
+CFATTACH_DECL_NEW(awin_ir, sizeof(struct awin_ir_softc),
+       awin_ir_match, awin_ir_attach, NULL, NULL);
+
+static int
+awin_ir_match(device_t parent, cfdata_t cf, void *aux)
+{
+       struct awinio_attach_args * const aio = aux;
+       const struct awin_locators * const loc = &aio->aio_loc;
+
+       if (strcmp(cf->cf_name, loc->loc_name))
+               return 0;
+
+       return 1;
+}
+
+static void
+awin_ir_attach(device_t parent, device_t self, void *aux)
+{
+       struct awin_ir_softc *sc = device_private(self);
+       struct awinio_attach_args * const aio = aux;
+       const struct awin_locators * const loc = &aio->aio_loc;
+       struct ir_attach_args iaa;
+
+       sc->sc_dev = self;
+       sc->sc_bst = aio->aio_core_bst;
+       mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_IR);
+       cv_init(&sc->sc_cv, "awinir");
+       bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
+           loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
+       aprint_naive("\n");
+       aprint_normal(": IR\n");
+
+       sc->sc_ih = intr_establish(loc->loc_intr, IPL_IR, IST_LEVEL,
+           awin_ir_intr, sc);
+       if (sc->sc_ih == NULL) {
+               aprint_error_dev(self, "couldn't establish interrupt %d\n",
+                   loc->loc_intr);
+               return;
+       }
+       aprint_normal_dev(self, "interrupting on irq %d\n", loc->loc_intr);
+
+       awin_ir_init(sc, aio);
+
+       memset(&iaa, 0, sizeof(iaa));
+       iaa.ia_type = IR_TYPE_CIR;
+       iaa.ia_methods = &awin_ir_methods;
+       iaa.ia_handle = sc;
+       sc->sc_cirdev = config_found_ia(self, "irbus", &iaa, ir_print);
+}
+
+static void
+awin_ir_init(struct awin_ir_softc *sc, struct awinio_attach_args * const aio)
+{
+       if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+               const struct awin_gpio_pinset pinset =
+                   { 'L', AWIN_A31_PIO_PL_IR_FUNC, AWIN_A31_PIO_PL_IR_PINS,
+                          GPIO_PIN_PULLUP };
+               bus_space_handle_t prcm_bsh;
+               bus_size_t prcm_size = 0x200;
+               uint32_t clk, reset, gating;
+               
+               bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
+                   AWIN_A31_PRCM_OFFSET, prcm_size, &prcm_bsh);
+
+               awin_gpio_pinset_acquire(&pinset);
+
+               gating = bus_space_read_4(sc->sc_bst, prcm_bsh,
+                   AWIN_A31_PRCM_APB0_GATING_REG);
+               gating |= AWIN_A31_PRCM_APB0_GATING_CIR;
+               bus_space_write_4(sc->sc_bst, prcm_bsh,
+                   AWIN_A31_PRCM_APB0_GATING_REG, gating);
+
+               reset = bus_space_read_4(sc->sc_bst, prcm_bsh,
+                   AWIN_A31_PRCM_APB0_RESET_REG);
+               reset |= AWIN_A31_PRCM_APB0_RESET_CIR;
+               bus_space_write_4(sc->sc_bst, prcm_bsh,
+                   AWIN_A31_PRCM_APB0_RESET_REG, reset);
+
+               clk = bus_space_read_4(sc->sc_bst, prcm_bsh,
+                   AWIN_A31_PRCM_CIR_CLK_REG);
+               clk &= ~AWIN_CLK_SRC_SEL;
+               clk |= 1;       /* HOSC */
+               clk &= ~AWIN_CLK_DIV_RATIO_M;
+               clk |= 7;       /* (24MHz / 3MHz) - 1 */
+               clk &= ~AWIN_CLK_DIV_RATIO_N;
+               clk |= 0;       /* 1 - 1 */
+               clk |= AWIN_CLK_ENABLE;
+               bus_space_write_4(sc->sc_bst, prcm_bsh,
+                   AWIN_A31_PRCM_CIR_CLK_REG, clk);
+
+               bus_space_unmap(sc->sc_bst, prcm_bsh, prcm_size);
+       }
+}
+
+static int
+awin_ir_intr(void *priv)
+{
+       struct awin_ir_softc *sc = priv;
+       uint32_t sta;
+
+       sta = IR_READ(sc, AWIN_IR_RXSTA_REG);
+
+       printf("%s: sta = 0x%08x\n", __func__, sta);
+
+       if ((sta & AWIN_IR_RXSTA_MASK) == 0)
+               return 0;
+
+       IR_WRITE(sc, AWIN_IR_RXSTA_REG, sta & AWIN_IR_RXSTA_MASK);
+
+       if (sta & AWIN_IR_RXSTA_RA) {
+               mutex_enter(&sc->sc_lock);
+               sc->sc_avail = __SHIFTOUT(sta, AWIN_IR_RXSTA_RAC);
+               cv_broadcast(&sc->sc_cv);
+               mutex_exit(&sc->sc_lock);
+       }
+
+       return 1;
+}
+
+static int
+awin_ir_open(void *priv, int flag, int mode, struct proc *p)
+{
+       struct awin_ir_softc *sc = priv;
+       uint32_t ctl, rxint;
+
+       ctl = __SHIFTIN(AWIN_IR_CTL_MD_CIR, AWIN_IR_CTL_MD);
+       IR_WRITE(sc, AWIN_IR_CTL_REG, ctl);
+
+       IR_WRITE(sc, AWIN_IR_RXCTL_REG, AWIN_IR_RXCTL_RPPI);
+
+       IR_WRITE(sc, AWIN_IR_RXSTA_REG, AWIN_IR_RXSTA_MASK);
+
+       rxint = AWIN_IR_RXINT_RAI_EN;
+       rxint |= __SHIFTIN(0, AWIN_IR_RXINT_RAL);
+       IR_WRITE(sc, AWIN_IR_RXINT_REG, rxint);
+
+       ctl |= AWIN_IR_CTL_GEN;
+       ctl |= AWIN_IR_CTL_RXEN;
+       IR_WRITE(sc, AWIN_IR_CTL_REG, ctl);
+
+       return 0;
+}
+
+static int
+awin_ir_close(void *priv, int flag, int mode, struct proc *p)
+{
+       struct awin_ir_softc *sc = priv;
+
+       IR_WRITE(sc, AWIN_IR_RXINT_REG, 0);
+       IR_WRITE(sc, AWIN_IR_CTL_REG, 0);
+       sc->sc_avail = 0;
+
+       return 0;
+}
+
+static int
+awin_ir_read(void *priv, struct uio *uio, int flag)
+{
+       struct awin_ir_softc *sc = priv;
+       uint8_t data;
+       int error = 0;
+
+       mutex_enter(&sc->sc_lock);
+       while (uio->uio_resid > 0) {
+               if (sc->sc_avail == 0) {
+                       error = cv_wait_sig(&sc->sc_cv, &sc->sc_lock);
+                       if (error) {
+                               break;
+                       }
+               }
+               if (sc->sc_avail > 0) {
+                       --sc->sc_avail;
+                       data = IR_READ(sc, AWIN_IR_RXFIFO_REG) &
+                           AWIN_IR_RXFIFO_DATA;
+                       error = uiomove(&data, sizeof(data), uio);
+                       if (error) {
+                               break;
+                       }



Home | Main Index | Thread Index | Old Index