[src/trunk]: src/sys/arch/arm/allwinner setup DRQ_CLR_CNT reg, clear FIR_VER ...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/dd667d12d5c1
branches:  trunk
changeset: 332082:dd667d12d5c1
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Sep 06 12:49:31 2014 +0000

description:
setup DRQ_CLR_CNT reg, clear FIR_VER bit, be more relaxed about blocksize, and set SRC DRQ TYPE for dma channel

diffstat:

 sys/arch/arm/allwinner/awin_ac.c |  16 ++++++++++------
 1 files changed, 10 insertions(+), 6 deletions(-)

diffs (63 lines):

diff -r 110edbe7607a -r dd667d12d5c1 sys/arch/arm/allwinner/awin_ac.c
--- a/sys/arch/arm/allwinner/awin_ac.c  Sat Sep 06 12:48:22 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_ac.c  Sat Sep 06 12:49:31 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_ac.c,v 1.3 2014/09/06 10:36:53 jmcneill Exp $ */
+/* $NetBSD: awin_ac.c,v 1.4 2014/09/06 12:49:31 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: awin_ac.c,v 1.3 2014/09/06 10:36:53 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: awin_ac.c,v 1.4 2014/09/06 12:49:31 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -45,8 +45,8 @@
 #include <arm/allwinner/awin_reg.h>
 #include <arm/allwinner/awin_var.h>
 
-#define AWINAC_TX_TRIG_LEVEL   64
-#define AWINAC_TX_MAX_LEVEL    128
+#define AWINAC_TX_TRIG_LEVEL   0xf
+#define AWINAC_DRQ_CLR_CNT     0x3
 #define AWINAC_INIT_VOL                0x3b
 
 #define AC_DAC_DPC             0x00
@@ -465,12 +465,14 @@
                return EINVAL;
 
        val = AC_READ(sc, AC_DAC_FIFOC);
-       val |= DAC_FIFOC_FIR_VER;
+       val &= ~DAC_FIFOC_FIR_VER;
        val &= ~DAC_FIFOC_FS;
        val |= __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS);
        val &= ~DAC_FIFOC_SEND_LASAT;
        val &= ~DAC_FIFOC_FIFO_MODE;
        val |= __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE);
+       val &= ~DAC_FIFOC_DRQ_CLR_CNT;
+       val |= __SHIFTIN(AWINAC_DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT);
        val &= ~DAC_FIFOC_TX_TRIG_LEVEL;
        val |= __SHIFTIN(AWINAC_TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL);
        val &= ~DAC_FIFOC_ADDA_LOOP_EN;
@@ -615,7 +617,7 @@
 awinac_round_blocksize(void *priv, int bs, int mode,
     const audio_params_t *params)
 {
-       return (bs + AWINAC_TX_MAX_LEVEL) & ~(AWINAC_TX_MAX_LEVEL-1);
+       return bs & ~3;
 }
 
 static size_t
@@ -668,6 +670,8 @@
        dmacfg |= AWIN_NDMA_CTL_DST_ADDR_NOINCR;
        dmacfg |= __SHIFTIN(AWIN_NDMA_CTL_DRQ_CODEC,
                            AWIN_DMA_CTL_DST_DRQ_TYPE);
+       dmacfg |= __SHIFTIN(AWIN_NDMA_CTL_DRQ_SDRAM,
+                           AWIN_DMA_CTL_SRC_DRQ_TYPE);
        awin_dma_set_config(sc->sc_pdma, dmacfg);
 
        error = awinac_play(sc);