[src/trunk]: src/sys/arch/arm/allwinner wrap awin_mmc_idma_descriptor in ifnd...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/af2071182cd7
branches:  trunk
changeset: 332123:af2071182cd7
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Sep 07 22:06:36 2014 +0000

description:
wrap awin_mmc_idma_descriptor in ifndef _LOCORE

diffstat:

 sys/arch/arm/allwinner/awin_reg.h |  8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diffs (36 lines):

diff -r 21c23f70bee3 -r af2071182cd7 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Sun Sep 07 21:54:08 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Sun Sep 07 22:06:36 2014 +0000
@@ -156,10 +156,16 @@
 /* A10/A20 SRAM Controller */
 #define AWIN_SRAM_CTL0_REG             0x0000
 #define AWIN_SRAM_CTL1_REG             0x0004
+#define AWIN_SRAM_VER_REG              0x0024
 
 #define AWIN_SRAM_CTL1_A3_A4           __BITS(5,4)
 #define AWIN_SRAM_CTL1_A3_A4_EMAC      1
 
+#define AWIN_SRAM_VER_KEY_FIELD                __BITS(31,16)
+#define AWIN_SRAM_VER_R_EN             __BIT(15)
+#define AWIN_SRAM_VER_BOOT_SEL_PAD_STA __BIT(8)
+#define AWIN_SRAM_VER_BITS             __BITS(7,0)
+
 /* A10/A20 DRAM Controller */
 #define AWIN_DRAM_CCR_REG              0x0000
 #define AWIN_DRAM_DCR_REG              0x0004
@@ -719,6 +725,7 @@
 #define AWIN_MMC_IDST_RECEIVE_INT      __BIT(1)
 #define AWIN_MMC_IDST_TRANSMIT_INT     __BIT(0)
 
+#if !defined(_LOCORE)
 struct awin_mmc_idma_descriptor {
        uint32_t        dma_config;
 #define AWIN_MMC_IDMA_CONFIG_DIC       __BIT(1)
@@ -732,6 +739,7 @@
        uint32_t        dma_buf_addr;
        uint32_t        dma_next;
 } __packed;
+#endif
 
 #define AWIN_CPUCFG_CPU0_RST_CTRL_REG  0x0040
 #define AWIN_CPUCFG_CPU0_CTRL_REG      0x0044