[src/trunk]: src/sys/arch/arm/arm32 Post a dmb before invalidating the cache ...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d98c610f66d9
branches:  trunk
changeset: 333565:d98c610f66d9
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sun Nov 09 09:18:07 2014 +0000

description:
Post a dmb before invalidating the cache in the post-{read,write}
operations to ensure that any/all cachelines brought in via speculation
are really flushed.

diffstat:

 sys/arch/arm/arm32/bus_dma.c |  6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diffs (32 lines):

diff -r 5cef26994bf8 -r d98c610f66d9 sys/arch/arm/arm32/bus_dma.c
--- a/sys/arch/arm/arm32/bus_dma.c      Sun Nov 09 00:05:06 2014 +0000
+++ b/sys/arch/arm/arm32/bus_dma.c      Sun Nov 09 09:18:07 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bus_dma.c,v 1.88 2014/10/18 08:33:24 snj Exp $ */
+/*     $NetBSD: bus_dma.c,v 1.89 2014/11/09 09:18:07 skrll Exp $       */
 
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
 #include "opt_arm_bus_space.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.88 2014/10/18 08:33:24 snj Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.89 2014/11/09 09:18:07 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -832,11 +832,13 @@
         */
        case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE:
                STAT_INCR(sync_postreadwrite);
+               __asm __volatile("dmb" ::: "memory");;
                cpu_dcache_inv_range(va, len);
                cpu_sdcache_inv_range(va, pa, len);
                break;
        case BUS_DMASYNC_POSTREAD:
                STAT_INCR(sync_postread);
+               __asm __volatile("dmb" ::: "memory");;
                cpu_dcache_inv_range(va, len);
                cpu_sdcache_inv_range(va, pa, len);
                break;