[src/trunk]: src/sys/arch/x86/include Add new cache descriptor (0xc3) from th...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/aaee56cbe2c4
branches:  trunk
changeset: 332167:aaee56cbe2c4
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Tue Sep 09 15:11:33 2014 +0000

description:
Add new cache descriptor (0xc3) from the latest Intel SDM.

diffstat:

 sys/arch/x86/include/cacheinfo.h |  3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diffs (17 lines):

diff -r a73f8806194b -r aaee56cbe2c4 sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h  Tue Sep 09 15:09:16 2014 +0000
+++ b/sys/arch/x86/include/cacheinfo.h  Tue Sep 09 15:11:33 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cacheinfo.h,v 1.18 2014/07/03 17:24:33 msaitoh Exp $   */
+/*     $NetBSD: cacheinfo.h,v 1.19 2014/09/09 15:11:33 msaitoh Exp $   */
 
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
@@ -247,6 +247,7 @@
 __CI_TBL(CAI_DTLB2,    0xc0,    4,  8,        4 * 1024, "4K/4M: 8 entries"), \
 __CI_TBL(CAI_L2_STLB2, 0xc1,    8,1024,       4 * 1024, "4K/2M: 1024 entries"), \
 __CI_TBL(CAI_DTLB2,    0xc2,    4, 16,        4 * 1024, "4K/2M: 16 entries"), \
+__CI_TBL(CAI_L2_STLB,  0xc3,    6,1536,       4 * 1024, NULL), \
 __CI_TBL(CAI_L2_STLB,  0xca,    4,512,        4 * 1024, NULL), \
 __CI_TBL(CAI_ICACHE,   0x06,    4,        8 * 1024, 32, NULL), \
 __CI_TBL(CAI_ICACHE,   0x08,    4,       16 * 1024, 32, NULL), \