[src/trunk]: src/sys/arch/arm/arm Don't flush random ASIDs. Instead always as...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e85100b6cdf4
branches:  trunk
changeset: 333329:e85100b6cdf4
user:      skrll <skrll%NetBSD.org@localhost>
date:      Wed Oct 29 16:22:31 2014 +0000

description:
Don't flush random ASIDs. Instead always assume KERNEL_PID, i.e. 0.
All other TLB flushes are done via

        pmap_tlb_invalidate_addr -> tlb_invalidate_addr

OK matt@

diffstat:

 sys/arch/arm/arm/cpufunc_asm_arm11.S |  11 +++++++----
 sys/arch/arm/arm/cpufunc_asm_armv7.S |   5 +----
 sys/arch/arm/arm/cpufunc_asm_pj4b.S  |   3 ++-
 3 files changed, 10 insertions(+), 9 deletions(-)

diffs (71 lines):

diff -r 32bb872e71cb -r e85100b6cdf4 sys/arch/arm/arm/cpufunc_asm_arm11.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm11.S      Wed Oct 29 16:14:45 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm11.S      Wed Oct 29 16:22:31 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm11.S,v 1.16 2014/10/29 16:14:45 skrll Exp $     */
+/*     $NetBSD: cpufunc_asm_arm11.S,v 1.17 2014/10/29 16:22:31 skrll Exp $     */
 
 /*
  * Copyright (c) 2002, 2005 ARM Limited
@@ -97,7 +97,8 @@
 
 ENTRY(arm11_tlb_flushI_SE)
 #ifdef ARM_MMU_EXTENDED
-       orr     r0, r0, r1              /* insert ASID into MVA */
+       bic     r0, r0, #0xff
+       bic     r0, r0, #0xf00          /* Always KERNEL_PID, i.e. 0 */
 #endif
        mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
 #if PAGE_SIZE == 2 * L2_S_SIZE
@@ -119,7 +120,8 @@
 
 ENTRY(arm11_tlb_flushD_SE)
 #ifdef ARM_MMU_EXTENDED
-       orr     r0, r0, r1              /* insert ASID into MVA */
+       bic     r0, r0, #0xff
+       bic     r0, r0, #0xf00          /* Always KERNEL_PID, i.e. 0 */
 #endif
        mcr     p15, 0, r0, c8, c6, 1   /* flush D tlb single entry */
 #if PAGE_SIZE == 2 * L2_S_SIZE
@@ -140,7 +142,8 @@
 
 ENTRY(arm11_tlb_flushID_SE)
 #ifdef ARM_MMU_EXTENDED
-       orr     r0, r0, r1              /* insert ASID into MVA */
+       bic     r0, r0, #0xff
+       bic     r0, r0, #0xf00          /* Always KERNEL_PID, i.e. 0 */
 #endif
        mcr     p15, 0, r0, c8, c7, 1   /* flush I+D tlb single entry */
 #if PAGE_SIZE == 2 * L2_S_SIZE
diff -r 32bb872e71cb -r e85100b6cdf4 sys/arch/arm/arm/cpufunc_asm_armv7.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv7.S      Wed Oct 29 16:14:45 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv7.S      Wed Oct 29 16:22:31 2014 +0000
@@ -78,10 +78,7 @@
 STRONG_ALIAS(armv7_tlb_flushD_SE, armv7_tlb_flushID_SE)
 STRONG_ALIAS(armv7_tlb_flushI_SE, armv7_tlb_flushID_SE)
 ENTRY(armv7_tlb_flushID_SE)
-       bfc     r0, #0, #12             @ clear ASID
-#ifdef ARM_MMU_EXTENDED
-       bfi     r0, r1, #0, #8          @ insert ASID into MVA
-#endif
+       bfc     r0, #0, #12             @ Always KERNEL_PID, i.e. 0
 #ifdef MULTIPROCESSOR
        mcr     p15, 0, r0, c8, c3, 1   @ flush I+D tlb single entry
 #if PAGE_SIZE == 2*L2_S_SIZE
diff -r 32bb872e71cb -r e85100b6cdf4 sys/arch/arm/arm/cpufunc_asm_pj4b.S
--- a/sys/arch/arm/arm/cpufunc_asm_pj4b.S       Wed Oct 29 16:14:45 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_pj4b.S       Wed Oct 29 16:22:31 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_pj4b.S,v 1.4 2014/03/30 01:15:03 matt Exp $ */
+/*     $NetBSD: cpufunc_asm_pj4b.S,v 1.5 2014/10/29 16:22:31 skrll Exp $ */
 
 /*******************************************************************************
 Copyright (C) Marvell International Ltd. and its affiliates
@@ -78,6 +78,7 @@
 END(pj4b_tlb_flushID)
 
 ENTRY(pj4b_tlb_flushID_SE)
+       bfc     r0, #0, #12             @ always KERNEL_PID (i.e. 0)
        mcr     p15, 0, r0, c8, c7, 1   @flush I+D tlb single entry
 #if PAGE_SIZE == 2 * L2_S_SIZE
        add     r0, r0, L2_S_SIZE