Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/arm/allwinner awin framebuffer support, not sure if...
details: https://anonhg.NetBSD.org/src/rev/9c2958b17da6
branches: trunk
changeset: 333568:9c2958b17da6
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Nov 09 14:10:54 2014 +0000
description:
awin framebuffer support, not sure if this works yet because hdmi is not working yet
diffstat:
sys/arch/arm/allwinner/awin_board.c | 97 ++++++++++-
sys/arch/arm/allwinner/awin_debe.c | 301 ++++++++++++++++++++++++++++++++++
sys/arch/arm/allwinner/awin_fb.c | 195 ++++++++++++++++++++++
sys/arch/arm/allwinner/awin_hdmi.c | 314 ++++++++++++++++++++++++++++-------
sys/arch/arm/allwinner/awin_io.c | 10 +-
sys/arch/arm/allwinner/awin_reg.h | 196 ++++++++++++++++++++++-
sys/arch/arm/allwinner/awin_tcon.c | 249 ++++++++++++++++++++++++++++
sys/arch/arm/allwinner/awin_var.h | 21 ++-
sys/arch/arm/allwinner/files.awin | 16 +-
9 files changed, 1316 insertions(+), 83 deletions(-)
diffs (truncated from 1672 to 300 lines):
diff -r 45fd4f339796 -r 9c2958b17da6 sys/arch/arm/allwinner/awin_board.c
--- a/sys/arch/arm/allwinner/awin_board.c Sun Nov 09 10:10:08 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_board.c Sun Nov 09 14:10:54 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_board.c,v 1.25 2014/10/29 14:14:14 skrll Exp $ */
+/* $NetBSD: awin_board.c,v 1.26 2014/11/09 14:10:54 jmcneill Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -36,7 +36,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.25 2014/10/29 14:14:14 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_board.c,v 1.26 2014/11/09 14:10:54 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -323,18 +323,25 @@
*/
const uint32_t ocfg = bus_space_read_4(bst, bsh,
AWIN_CCM_OFFSET + AWIN_PLL6_CFG_REG);
- const u_int k = __SHIFTOUT(ocfg, AWIN_PLL_CFG_FACTOR_K);
/*
* Output freq is 24MHz * n * k / m / 6.
* To get to 100MHz, k & m must be equal and n must be 25.
*/
uint32_t ncfg = ocfg;
- ncfg &= ~(AWIN_PLL_CFG_FACTOR_M|AWIN_PLL_CFG_FACTOR_N);
ncfg &= ~(AWIN_PLL_CFG_BYPASS);
- ncfg |= __SHIFTIN(k, AWIN_PLL_CFG_FACTOR_M);
- ncfg |= __SHIFTIN(25, AWIN_PLL_CFG_FACTOR_N);
- ncfg |= AWIN_PLL_CFG_ENABLE | AWIN_PLL6_CFG_SATA_CLK_EN;
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ ncfg &= ~(AWIN_PLL_CFG_FACTOR_N|AWIN_PLL_CFG_FACTOR_K);
+ ncfg |= __SHIFTIN(1, AWIN_PLL_CFG_FACTOR_K);
+ ncfg |= __SHIFTIN(24, AWIN_PLL_CFG_FACTOR_N);
+ } else {
+ const u_int k = __SHIFTOUT(ocfg, AWIN_PLL_CFG_FACTOR_K);
+ ncfg &= ~(AWIN_PLL_CFG_FACTOR_M|AWIN_PLL_CFG_FACTOR_N);
+ ncfg |= __SHIFTIN(k, AWIN_PLL_CFG_FACTOR_M);
+ ncfg |= __SHIFTIN(25, AWIN_PLL_CFG_FACTOR_N);
+ ncfg |= AWIN_PLL6_CFG_SATA_CLK_EN;
+ }
+ ncfg |= AWIN_PLL_CFG_ENABLE;
if (ncfg != ocfg) {
bus_space_write_4(bst, bsh,
AWIN_CCM_OFFSET + AWIN_PLL6_CFG_REG, ncfg);
@@ -387,6 +394,40 @@
}
void
+awin_pll3_enable(void)
+{
+ bus_space_tag_t bst = &awin_bs_tag;
+ bus_space_handle_t bsh = awin_core_bsh;
+
+ /*
+ * HDMI needs PLL3 to be 29700000 Hz
+ */
+ const uint32_t ocfg = bus_space_read_4(bst, bsh,
+ AWIN_CCM_OFFSET + AWIN_PLL3_CFG_REG);
+
+ uint32_t ncfg = ocfg;
+
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ ncfg &= ~AWIN_A31_PLL3_CFG_MODE;
+ ncfg &= ~AWIN_A31_PLL3_CFG_MODE_SEL;
+ ncfg |= AWIN_A31_PLL3_CFG_FRAC_CLK_OUT;
+ /* 24MHz*N/M - for 29.7MHz, N=99, M=8 */
+ ncfg |= __SHIFTIN(98, AWIN_A31_PLL3_CFG_FACTOR_N);
+ ncfg |= __SHIFTIN(7, AWIN_A31_PLL3_CFG_PREDIV_M);
+ ncfg |= AWIN_PLL_CFG_ENABLE;
+ } else {
+ ncfg &= ~AWIN_PLL3_MODE_SEL;
+ ncfg |= AWIN_PLL3_FRAC_SET;
+ ncfg |= AWIN_PLL_CFG_ENABLE;
+ }
+
+ if (ncfg != ocfg) {
+ bus_space_write_4(bst, bsh,
+ AWIN_CCM_OFFSET + AWIN_PLL3_CFG_REG, ncfg);
+ }
+}
+
+void
awin_pll7_enable(void)
{
bus_space_tag_t bst = &awin_bs_tag;
@@ -401,8 +442,14 @@
uint32_t ncfg = ocfg;
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ ncfg &= ~AWIN_A31_PLL7_CFG_MODE;
ncfg &= ~AWIN_A31_PLL7_CFG_MODE_SEL;
ncfg |= AWIN_A31_PLL7_CFG_FRAC_CLK_OUT;
+ /* 24MHz*N/M - for 29.7MHz, N=99, M=8 */
+ ncfg &= ~AWIN_A31_PLL7_CFG_FACTOR_N;
+ ncfg &= ~AWIN_A31_PLL7_CFG_PREDIV_M;
+ ncfg |= __SHIFTIN(98, AWIN_A31_PLL7_CFG_FACTOR_N);
+ ncfg |= __SHIFTIN(7, AWIN_A31_PLL7_CFG_PREDIV_M);
ncfg |= AWIN_PLL_CFG_ENABLE;
} else {
ncfg &= ~AWIN_PLL7_MODE_SEL;
@@ -415,3 +462,39 @@
AWIN_CCM_OFFSET + AWIN_PLL7_CFG_REG, ncfg);
}
}
+
+void
+awin_pll3_set_rate(uint32_t rate)
+{
+ bus_space_tag_t bst = &awin_bs_tag;
+ bus_space_handle_t bsh = awin_core_bsh;
+
+ const uint32_t ocfg = bus_space_read_4(bst, bsh,
+ AWIN_CCM_OFFSET + AWIN_PLL3_CFG_REG);
+
+ uint32_t ncfg = ocfg;
+ if (rate == 0) {
+ ncfg &= ~AWIN_PLL_CFG_ENABLE;
+ } else {
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ unsigned int m = rate / 3000000;
+ ncfg |= AWIN_PLL3_MODE_SEL;
+ ncfg &= ~AWIN_PLL3_FACTOR_M;
+ ncfg |= __SHIFTIN(m, AWIN_PLL3_FACTOR_M);
+ } else {
+ unsigned int m = 8;
+ unsigned int n = rate / 3000000;
+ ncfg |= AWIN_A31_PLL3_CFG_MODE_SEL;
+ ncfg &= ~AWIN_A31_PLL3_CFG_FACTOR_N;
+ ncfg |= __SHIFTIN(n - 1, AWIN_A31_PLL3_CFG_FACTOR_N);
+ ncfg &= ~AWIN_A31_PLL3_CFG_PREDIV_M;
+ ncfg |= __SHIFTIN(m - 1, AWIN_A31_PLL3_CFG_PREDIV_M);
+ }
+ ncfg |= AWIN_PLL_CFG_ENABLE;
+ }
+
+ if (ncfg != ocfg) {
+ bus_space_write_4(bst, bsh,
+ AWIN_CCM_OFFSET + AWIN_PLL3_CFG_REG, ncfg);
+ }
+}
diff -r 45fd4f339796 -r 9c2958b17da6 sys/arch/arm/allwinner/awin_debe.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/allwinner/awin_debe.c Sun Nov 09 14:10:54 2014 +0000
@@ -0,0 +1,301 @@
+/* $NetBSD: awin_debe.c,v 1.1 2014/11/09 14:10:54 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef AWIN_DEBE_VIDEOMEM
+#define AWIN_DEBE_VIDEOMEM (16 * 1024 * 1024)
+#endif
+
+#include "genfb.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: awin_debe.c,v 1.1 2014/11/09 14:10:54 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+
+#include <arm/allwinner/awin_reg.h>
+#include <arm/allwinner/awin_var.h>
+
+#include <dev/videomode/videomode.h>
+
+struct awin_debe_softc {
+ device_t sc_dev;
+ device_t sc_fbdev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ bus_space_handle_t sc_ccm_bsh;
+ bus_dma_tag_t sc_dmat;
+ unsigned int sc_port;
+
+ bus_dma_segment_t sc_dmasegs[1];
+ bus_size_t sc_dmasize;
+ bus_dmamap_t sc_dmamap;
+ void *sc_dmap;
+};
+
+#define DEBE_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define DEBE_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+
+static int awin_debe_match(device_t, cfdata_t, void *);
+static void awin_debe_attach(device_t, device_t, void *);
+
+static int awin_debe_alloc_videomem(struct awin_debe_softc *);
+static void awin_debe_setup_fbdev(struct awin_debe_softc *,
+ struct videomode *);
+
+CFATTACH_DECL_NEW(awin_debe, sizeof(struct awin_debe_softc),
+ awin_debe_match, awin_debe_attach, NULL, NULL);
+
+static int
+awin_debe_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct awinio_attach_args * const aio = aux;
+ const struct awin_locators * const loc = &aio->aio_loc;
+
+ if (strcmp(cf->cf_name, loc->loc_name))
+ return 0;
+
+ return 1;
+}
+
+static void
+awin_debe_attach(device_t parent, device_t self, void *aux)
+{
+ struct awin_debe_softc *sc = device_private(self);
+ struct awinio_attach_args * const aio = aux;
+ const struct awin_locators * const loc = &aio->aio_loc;
+ int error;
+
+ sc->sc_dev = self;
+ sc->sc_bst = aio->aio_core_bst;
+ sc->sc_dmat = aio->aio_dmat;
+ sc->sc_port = loc->loc_port;
+ bus_space_subregion(sc->sc_bst, aio->aio_core_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+ bus_space_subregion(sc->sc_bst, aio->aio_ccm_bsh, 0, 0x1000,
+ &sc->sc_ccm_bsh);
+
+ aprint_naive("\n");
+ aprint_normal(": Display Engine Backend\n");
+
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_A31_AHB_RESET1_REG,
+ AWIN_A31_AHB_RESET1_BE0_RST << loc->loc_port,
+ 0);
+ }
+
+ if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_BE0_SCLK_CFG_REG + (loc->loc_port * 4),
+ __SHIFTIN(AWIN_A31_BEx_CLK_SRC_SEL_PLL6_2X,
+ AWIN_A31_BEx_CLK_SRC_SEL),
+ AWIN_A31_BEx_CLK_SRC_SEL);
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_BE0_SCLK_CFG_REG + (loc->loc_port * 4),
+ 4 - 1, AWIN_BEx_CLK_DIV_RATIO_M);
+ } else {
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_BE0_SCLK_CFG_REG + (loc->loc_port * 4),
+ AWIN_BEx_CLK_RST |
+ __SHIFTIN(AWIN_BEx_CLK_SRC_SEL_PLL5, AWIN_BEx_CLK_SRC_SEL),
+ AWIN_BEx_CLK_SRC_SEL);
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_BE0_SCLK_CFG_REG + (loc->loc_port * 4),
+ 0 /* XXX */, AWIN_BEx_CLK_DIV_RATIO_M);
+ }
+
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_DE_BE0 << loc->loc_port, 0);
+
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_DRAM_CLK_REG,
+ AWIN_DRAM_CLK_BE0_DCLK_ENABLE << loc->loc_port, 0);
+
+ awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+ AWIN_BE0_SCLK_CFG_REG + (loc->loc_port * 4),
+ AWIN_CLK_ENABLE, 0);
+
Home |
Main Index |
Thread Index |
Old Index