[src/trunk]: src/sys/arch/arm/allwinner fix some mixer processor definitions, ...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/3f9940565967
branches:  trunk
changeset: 334732:3f9940565967
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Thu Dec 04 02:11:03 2014 +0000

description:
fix some mixer processor definitions, add A31 PLL6 cfg lock bit and some extra SD CLK bits

diffstat:

 sys/arch/arm/allwinner/awin_reg.h |  19 +++++++++++++++----
 1 files changed, 15 insertions(+), 4 deletions(-)

diffs (59 lines):

diff -r bfa98447710e -r 3f9940565967 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Thu Dec 04 01:41:37 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Thu Dec 04 02:11:03 2014 +0000
@@ -1076,6 +1076,10 @@
 #define AWIN_CLK_SRC_SEL_DE_PLL5       2
 #define AWIN_CLK_SRC_SEL_CIR_LOSC      0
 #define AWIN_CLK_SRC_SEL_CIR_HOSC      1
+#define AWIN_CLK_SRC_SEL_MP_PLL3       0
+#define AWIN_CLK_SRC_SEL_MP_PLL7       1
+#define AWIN_CLK_SRC_SEL_MP_PLL9       2
+#define AWIN_CLK_SRC_SEL_MP_PLL10      3
 #define AWIN_CLK_DIV_RATIO_N           __BITS(17,16)
 #define AWIN_CLK_DIV_RATIO_M           __BITS(3,0)
 
@@ -1141,8 +1145,13 @@
 #define AWIN_HDMI_CLK_SRC_SEL_PLL7_2X  3
 #define AWIN_HDMI_CLK_DIV_RATIO_M      __BITS(3,0)
 
+#define AWIN_SD_CLK_SRC_SEL            __BITS(25,24)
+#define AWIN_SD_CLK_SRC_SEL_OSC24M     0
+#define AWIN_SD_CLK_SRC_SEL_PLL6       1
 #define AWIN_SD_CLK_PHASE_CTR          __BITS(22,20)
+#define AWIN_SD_CLK_DIV_RATIO_N                __BITS(17,16)
 #define AWIN_SD_CLK_OUTPUT_PHASE_CTR   __BITS(10,8)
+#define AWIN_SD_CLK_DIV_RATIO_M                __BITS(3,0)
 
 #define AWIN_CLK_OUT_ENABLE            __BIT(31)
 #define AWIN_CLK_OUT_SRC_SEL           __BITS(25,24)
@@ -2024,7 +2033,7 @@
 /* Mixer processor */
 #define AWIN_MP_CTL_REG                                0x0000
 #define AWIN_MP_STS_REG                                0x0004
-#define AWIN_MP_IDMAGBLCTL_REG                 0x0008
+#define AWIN_MP_IDMAGLBCTL_REG                 0x0008
 #define AWIN_MP_IDMA_H4ADD_REG                 0x000C
 #define AWIN_MP_IDMA_L32ADD_REG(n)             (0x0010 + ((n) * 4))
 #define AWIN_MP_IDMALINEWIDTH_REG(n)           (0x0020 + ((n) * 4))
@@ -2111,9 +2120,9 @@
 #define AWIN_MP_IDMASET_IDMA_FCMODEN           __BIT(16)
 #define AWIN_MP_IDMASET_IDMA_PS                        __BITS(15,12)
 #define AWIN_MP_IDMASET_IDMA_FMT               __BITS(11,8)
-#define AWIN_MP_IDMASET_IDMA_FMT_ARGB888       0
-#define AWIN_MP_IDMASET_IDMA_FMT_ARGB444       1
-#define AWIN_MP_IDMASET_IDMA_FMT_ARGB155       2
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB8888      0
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB4444      1
+#define AWIN_MP_IDMASET_IDMA_FMT_ARGB1555      2
 #define AWIN_MP_IDMASET_IDMA_FMT_RGB565                3
 #define AWIN_MP_IDMASET_IDMA_FMT_IYUV422       4
 #define AWIN_MP_IDMASET_IDMA_FMT_UV88          5
@@ -2297,6 +2306,8 @@
 #define AWIN_A31_PLL3_CFG_FACTOR_N     __BITS(14,8)
 #define AWIN_A31_PLL3_CFG_PREDIV_M     __BITS(3,0)
 
+#define AWIN_A31_PLL6_CFG_LOCK         __BIT(28)
+
 #define AWIN_A31_PLL7_CFG_MODE         __BIT(30)
 #define AWIN_A31_PLL7_CFG_LOCK         __BIT(28)
 #define AWIN_A31_PLL7_CFG_FRAC_CLK_OUT __BIT(25)