[src/trunk]: src/sys/arch/x86 Use specialreg.h's definitions.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/3f5d00284b1d
branches:  trunk
changeset: 334862:3f5d00284b1d
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Dec 12 02:25:55 2014 +0000

description:
Use specialreg.h's definitions.

diffstat:

 sys/arch/x86/include/specialreg.h  |   3 ++-
 sys/arch/x86/x86/cpu_ucode_intel.c |  14 +++++---------
 2 files changed, 7 insertions(+), 10 deletions(-)

diffs (67 lines):

diff -r 3047b93253a4 -r 3f5d00284b1d sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Fri Dec 12 01:13:40 2014 +0000
+++ b/sys/arch/x86/include/specialreg.h Fri Dec 12 02:25:55 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.80 2014/09/11 18:11:59 msaitoh Exp $  */
+/*     $NetBSD: specialreg.h,v 1.81 2014/12/12 02:25:55 msaitoh Exp $  */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -506,6 +506,7 @@
 #define        MSR_CESR                0x011   /* P5 only (trap on P6) */
 #define        MSR_CTR0                0x012   /* P5 only (trap on P6) */
 #define        MSR_CTR1                0x013   /* P5 only (trap on P6) */
+#define MSR_IA32_PLATFORM_ID   0x017
 #define MSR_APICBASE           0x01b
 #define MSR_EBL_CR_POWERON     0x02a
 #define MSR_EBC_FREQUENCY_ID   0x02c   /* PIV only */
diff -r 3047b93253a4 -r 3f5d00284b1d sys/arch/x86/x86/cpu_ucode_intel.c
--- a/sys/arch/x86/x86/cpu_ucode_intel.c        Fri Dec 12 01:13:40 2014 +0000
+++ b/sys/arch/x86/x86/cpu_ucode_intel.c        Fri Dec 12 02:25:55 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_ucode_intel.c,v 1.5 2014/03/26 08:04:19 christos Exp $ */
+/* $NetBSD: cpu_ucode_intel.c,v 1.6 2014/12/12 02:25:55 msaitoh Exp $ */
 /*
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -29,7 +29,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_ucode_intel.c,v 1.5 2014/03/26 08:04:19 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_ucode_intel.c,v 1.6 2014/12/12 02:25:55 msaitoh Exp $");
 
 #include "opt_xen.h"
 #include "opt_cpu_ucode.h"
@@ -46,10 +46,6 @@
 #include <machine/specialreg.h>
 #include <x86/cpu_ucode.h>
 
-#define MSR_IA32_PLATFORM_ID 0x17
-#define MSR_IA32_BIOS_UPDT_TRIGGER 0x79
-#define MSR_IA32_BIOS_SIGN_ID 0x8b
-
 static void
 intel_getcurrentucode(uint32_t *ucodeversion, int *platformid)
 {
@@ -58,9 +54,9 @@
 
        kpreempt_disable();
 
-       wrmsr(MSR_IA32_BIOS_SIGN_ID, 0);
+       wrmsr(MSR_BIOS_SIGN, 0);
        x86_cpuid(0, unneeded_ids);
-       msr = rdmsr(MSR_IA32_BIOS_SIGN_ID);
+       msr = rdmsr(MSR_BIOS_SIGN);
        *ucodeversion = msr >> 32;
 
        kpreempt_enable();
@@ -138,7 +134,7 @@
                kpreempt_enable();
                return EEXIST; /* ??? */
        }
-       wrmsr(MSR_IA32_BIOS_UPDT_TRIGGER, (uintptr_t)(sc->sc_blob) + 48);
+       wrmsr(MSR_BIOS_UPDT_TRIG, (uintptr_t)(sc->sc_blob) + 48);
        intel_getcurrentucode(&nucodeversion, &platformid);
 
        kpreempt_enable();