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[src/trunk]: src/sys/arch/arm/samsung arch/arm/samsung/ cleanup : move SoC sp...
details: https://anonhg.NetBSD.org/src/rev/789a07baa434
branches: trunk
changeset: 332600:789a07baa434
user: reinoud <reinoud%NetBSD.org@localhost>
date: Tue Sep 30 14:23:41 2014 +0000
description:
arch/arm/samsung/ cleanup : move SoC specific power and phy routines into
exynos_soc.c and move Odroid board specific tweaks to odroid_machdep.c
diffstat:
sys/arch/arm/samsung/exynos_soc.c | 359 +++++++++++++++++++++++++++++++++++-
sys/arch/arm/samsung/exynos_usb.c | 362 +------------------------------------
sys/arch/arm/samsung/exynos_var.h | 13 +-
3 files changed, 364 insertions(+), 370 deletions(-)
diffs (truncated from 885 to 300 lines):
diff -r ef260264bfc2 -r 789a07baa434 sys/arch/arm/samsung/exynos_soc.c
--- a/sys/arch/arm/samsung/exynos_soc.c Tue Sep 30 14:20:55 2014 +0000
+++ b/sys/arch/arm/samsung/exynos_soc.c Tue Sep 30 14:23:41 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: exynos_soc.c,v 1.22 2014/09/30 12:55:29 reinoud Exp $ */
+/* $NetBSD: exynos_soc.c,v 1.23 2014/09/30 14:23:41 reinoud Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.22 2014/09/30 12:55:29 reinoud Exp $");
+__KERNEL_RCSID(1, "$NetBSD: exynos_soc.c,v 1.23 2014/09/30 14:23:41 reinoud Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -201,6 +201,7 @@
}
+#ifdef EXYNOS4
/*
* The latency values used below are `magic' and probably chosen empirically.
* For the 4210 variant the data latency is lower, a 0x110. This is currently
@@ -211,7 +212,7 @@
*/
int
-exynos_l2cc_init(void)
+exynos4_l2cc_init(void)
{
const uint32_t tag_latency = 0x110;
const uint32_t data_latency = IS_EXYNOS4410_P() ? 0x110 : 0x120;
@@ -268,6 +269,7 @@
return 0;
}
+#endif
#endif /* ARM_TRUSTZONE_FIRMWARE */
@@ -469,19 +471,6 @@
/* XXX clock stuff needs major work XXX */
-static void
-exynos_init_clkout_for_usb(void)
-{
-#ifdef EXYNOS4
- bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
- EXYNOS_PMU_DEBUG_CLKOUT, 0x900);
-#endif
-#ifdef EXYNOS5
- bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
- EXYNOS_PMU_DEBUG_CLKOUT, 0x1000);
-#endif
-}
-
void
exynos_clocks_bootstrap(void)
@@ -606,7 +595,7 @@
* XXX KLUDGE ALERT XXX
* The iot mainbus supplies is completely wrong since it scales
* addresses by 2. The simplest remedy is to replace with our
- * bus space used for the armcore regisers (which armperiph uses).
+ * bus space used for the armcore registers (which armperiph uses).
*/
struct mainbus_attach_args * const mb = aux;
mb->mb_iot = &exynos_bs_tag;
@@ -678,3 +667,339 @@
exyo_device_register_post_config(self, aux);
}
+
+/*
+ * USB power SoC dependent handling
+ */
+
+#ifdef EXYNOS4
+static struct exynos_gpio_pinset e4_uhost_pwr_pinset = {
+ .pinset_group = "ETC6",
+ .pinset_func = 0,
+ .pinset_mask = __BIT(6) | __BIT(7),
+};
+#endif
+
+
+#ifdef EXYNOS5
+static struct exynos_gpio_pinset e5_uhost_pwr_pinset = {
+ .pinset_group = "ETC6",
+ .pinset_func = 0,
+ .pinset_mask = __BIT(5) | __BIT(6),
+};
+static struct exynos_gpio_pinset e5_usb3_bus0_pinset = {
+ .pinset_group = "GPK3",
+ .pinset_func = 2,
+ .pinset_mask = __BIT(0) | __BIT(1) | __BIT(3),
+};
+static struct exynos_gpio_pinset e5_usb3_bus1_pinset = {
+ .pinset_group = "GPK2",
+ .pinset_func = 2,
+ .pinset_mask = __BIT(4) | __BIT(5) | __BIT(7),
+};
+#endif
+
+
+void
+exynos_usb_soc_powerup(void)
+{
+ struct exynos_gpio_pindata XuhostOVERCUR;
+ struct exynos_gpio_pindata XuhostPWREN;
+
+#ifdef EXYNOS4
+ exynos_gpio_pinset_acquire(&e4_uhost_pwr_pinset);
+ exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 6, &XuhostPWREN);
+ exynos_gpio_pinset_to_pindata(&e4_uhost_pwr_pinset, 7, &XuhostOVERCUR);
+
+ /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
+ exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
+ DELAY(80000);
+#endif
+#ifdef EXYNOS5
+ if (IS_EXYNOS5410_P()) {
+ struct exynos_gpio_pindata Xovercur2, Xovercur3;
+ struct exynos_gpio_pindata Xvbus;
+
+ /* BUS 0 */
+ exynos_gpio_pinset_acquire(&e5_usb3_bus0_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 0, &Xovercur2);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 1, &Xovercur3);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus0_pinset, 3, &Xvbus);
+
+ /* enable power and set overcur inactive by pulling them up */
+ exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP);
+
+ /* BUS 1 */
+ exynos_gpio_pinset_acquire(&e5_usb3_bus1_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 4, &Xovercur2);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 5, &Xovercur3);
+ exynos_gpio_pinset_to_pindata(&e5_usb3_bus1_pinset, 7, &Xvbus);
+
+ /* enable power and set overcur inactive by pulling them up */
+ exynos_gpio_pindata_ctl(&Xvbus, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur2, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&Xovercur3, GPIO_PIN_PULLUP);
+
+ /* enable power to the hub */
+ exynos_gpio_pinset_acquire(&e5_uhost_pwr_pinset);
+ exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 5, &XuhostPWREN);
+ exynos_gpio_pinset_to_pindata(&e5_uhost_pwr_pinset, 6, &XuhostOVERCUR);
+
+ /* enable power and set Xuhost OVERCUR to inactive by pulling it up */
+ exynos_gpio_pindata_ctl(&XuhostPWREN, GPIO_PIN_PULLUP);
+ exynos_gpio_pindata_ctl(&XuhostOVERCUR, GPIO_PIN_PULLUP);
+ DELAY(80000);
+ }
+ /* XXX 5422 XXX */
+#endif
+}
+
+
+/*
+ * USB Phy SoC dependent handling
+ */
+
+/* XXX 5422 not handled since its unknown how it handles this XXX*/
+static void
+exynos_usb2_set_isolation(bool on)
+{
+ uint32_t en_mask, regval;
+ bus_addr_t reg;
+
+ /* enable PHY */
+ reg = EXYNOS_PMU_USB_PHY_CTRL;
+
+ if (IS_EXYNOS5_P() || IS_EXYNOS4410_P()) {
+ /* set usbhost mode */
+ regval = on ? 0 : USB20_PHY_HOST_LINK_EN;
+ bus_space_write_4(&exynos_bs_tag, exynos_sysreg_bsh,
+ EXYNOS5_SYSREG_USB20_PHY_TYPE, regval);
+ reg = EXYNOS_PMU_USBHOST_PHY_CTRL;
+ }
+
+ /* do enable PHY */
+ en_mask = PMU_PHY_ENABLE;
+ regval = bus_space_read_4(&exynos_bs_tag, exynos_pmu_bsh, reg);
+ regval = on ? regval & ~en_mask : regval | en_mask;
+
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ reg, regval);
+
+ if (IS_EXYNOS4X12_P()) {
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ EXYNOS_PMU_USB_HSIC_1_PHY_CTRL, regval);
+ bus_space_write_4(&exynos_bs_tag, exynos_pmu_bsh,
+ EXYNOS_PMU_USB_HSIC_2_PHY_CTRL, regval);
+ }
+}
+
+
+#ifdef EXYNOS4
+static void
+exynos4_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
+{
+ uint32_t phypwr, rstcon, clkreg;
+
+ /* write clock value */
+ clkreg = FSEL_CLKSEL_24M;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYCLK, clkreg);
+
+ /* set device and host to normal */
+ phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR);
+
+ /* enable analog, enable otg, unsleep phy0 (host) */
+ phypwr &= ~PHYPWR_NORMAL_MASK_PHY0;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR, phypwr);
+
+ if (IS_EXYNOS4X12_P()) {
+ /* enable hsic0 (host), enable hsic1 and phy1 (otg) */
+ phypwr = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR);
+ phypwr &= ~(PHYPWR_NORMAL_MASK_HSIC0 |
+ PHYPWR_NORMAL_MASK_HSIC1 |
+ PHYPWR_NORMAL_MASK_PHY1);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHYPWR, phypwr);
+ }
+
+ /* reset both phy and link of device */
+ rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON);
+ rstcon |= RSTCON_DEVPHY_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ DELAY(10000);
+ rstcon &= ~RSTCON_DEVPHY_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+
+ if (IS_EXYNOS4X12_P()) {
+ /* reset both phy and link of host */
+ rstcon = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON);
+ rstcon |= RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST;
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ DELAY(10000);
+ rstcon &= ~(RSTCON_HOSTPHY_SWRST | RSTCON_HOSTPHYLINK_SWRST);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_RSTCON, rstcon);
+ }
+
+ /* wait for everything to be initialized */
+ DELAY(80000);
+}
+#endif
+
+
+#ifdef EXYNOS5
+static void
+exynos5410_usb2phy_enable(bus_space_handle_t usb2phy_bsh)
+{
+ uint32_t phyhost; //, phyotg;
+ uint32_t phyhsic1, phyhsic2, hsic_ctrl;
+ uint32_t ehcictrl; //, ohcictrl;
+
+ /* host configuration: */
+ phyhost = bus_space_read_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_CTRL0);
+
+ /* host phy reference clock; assumption its 24 MHz now */
+ phyhost &= ~HOST_CTRL0_FSEL_MASK;
+ phyhost |= __SHIFTIN(HOST_CTRL0_FSEL_MASK, FSEL_CLKSEL_24M);
+
+ /* enable normal mode of operation */
+ phyhost &= ~(HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP);
+
+ /* host phy reset */
+ phyhost &= ~(HOST_CTRL0_PHY_SWRST | HOST_CTRL0_PHY_SWRST_ALL |
+ HOST_CTRL0_SIDDQ | HOST_CTRL0_COMMONON_N);
+
+ /* host link reset */
+ phyhost |= HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST;
+
+ /* do the reset */
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_CTRL0, phyhost);
+ DELAY(10000);
+ phyhost &= ~(HOST_CTRL0_LINK_SWRST | HOST_CTRL0_UTMI_SWRST);
+ bus_space_write_4(&exynos_bs_tag, usb2phy_bsh,
+ USB_PHY_HOST_CTRL0, phyhost);
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