[src/trunk]: src/sys/arch/evbarm/awin When spinning up the 2nd CPU, do it in ...

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ac7dc61de4f7
branches:  trunk
changeset: 332507:ac7dc61de4f7
user:      matt <matt%NetBSD.org@localhost>
date:      Thu Sep 25 07:59:29 2014 +0000

description:
When spinning up the 2nd CPU, do it in little-endian mode so we access
the chip's registers properly.

diffstat:

 sys/arch/evbarm/awin/awin_start.S |  12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diffs (43 lines):

diff -r cc805d307aa2 -r ac7dc61de4f7 sys/arch/evbarm/awin/awin_start.S
--- a/sys/arch/evbarm/awin/awin_start.S Thu Sep 25 05:58:34 2014 +0000
+++ b/sys/arch/evbarm/awin/awin_start.S Thu Sep 25 07:59:29 2014 +0000
@@ -41,7 +41,7 @@
 #include <arm/allwinner/awin_reg.h>
 #include <evbarm/awin/platform.h>  
 
-RCSID("$NetBSD: awin_start.S,v 1.1 2014/08/31 19:13:01 matt Exp $")
+RCSID("$NetBSD: awin_start.S,v 1.2 2014/09/25 07:59:29 matt Exp $")
 
 #if defined(VERBOSE_INIT_ARM)
 #define        XPUTC(n)        mov r0, n; bl xputc
@@ -178,6 +178,10 @@
        movw    r5, #:lower16:(AWIN_CORE_PBASE+AWIN_CPUCFG_OFFSET)
        movt    r5, #:upper16:(AWIN_CORE_PBASE+AWIN_CPUCFG_OFFSET)
 
+#ifdef __ARMEB__
+       setend  le                      // everything here is little-endian
+#endif
+
        /* Set where the other CPU(s) are going to execute */
        movw    r1, #:lower16:cortex_mpstart
        movt    r1, #:upper16:cortex_mpstart
@@ -210,7 +214,7 @@
 
        /* We need to wait (at least) 10ms */
        mov     r0, #0x3b000                    // 10.06ms
-       bl      _C_LABEL(gtmr_bootdelay)
+       bl      _C_LABEL(gtmr_bootdelay)        // endian-neutral
 
        /* Clear power-off gating */
        ldr     r1, [r5, #AWIN_CPUCFG_CPU1_PWROFF_REG] 
@@ -230,6 +234,10 @@
        str     r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG]
        dsb
 
+#ifdef __ARMEB__
+       setend  be                              // we're done with little endian
+#endif
+
        //
        // Wait up a second for CPU1 to hatch. 
        //