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[src/trunk]: src/sys/arch/arm/allwinner ignore pending bits that arent enabled
details: https://anonhg.NetBSD.org/src/rev/9500ee6da94a
branches: trunk
changeset: 332994:9500ee6da94a
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Mon Oct 13 13:34:54 2014 +0000
description:
ignore pending bits that arent enabled
diffstat:
sys/arch/arm/allwinner/awin_dma_a31.c | 7 ++++---
sys/arch/arm/allwinner/awin_reg.h | 4 ++++
2 files changed, 8 insertions(+), 3 deletions(-)
diffs (45 lines):
diff -r 154b34d7fb4c -r 9500ee6da94a sys/arch/arm/allwinner/awin_dma_a31.c
--- a/sys/arch/arm/allwinner/awin_dma_a31.c Mon Oct 13 13:00:55 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_dma_a31.c Mon Oct 13 13:34:54 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_dma_a31.c,v 1.1 2014/10/13 12:34:00 jmcneill Exp $ */
+/* $NetBSD: awin_dma_a31.c,v 1.2 2014/10/13 13:34:54 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "opt_ddb.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: awin_dma_a31.c,v 1.1 2014/10/13 12:34:00 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: awin_dma_a31.c,v 1.2 2014/10/13 13:34:54 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -161,10 +161,11 @@
pend = pend0 | ((uint64_t)pend1 << 32);
- while ((bit = ffs64(pend)) != 0) {
+ while ((bit = ffs64(pend & AWIN_A31_DMA_IRQ_PKG_MASK)) != 0) {
mask = __BIT(bit - 1);
pend &= ~mask;
index = (bit - 1) / 4;
+
if (awin_dma_channels[index].ch_callback == NULL)
continue;
awin_dma_channels[index].ch_callback(
diff -r 154b34d7fb4c -r 9500ee6da94a sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Mon Oct 13 13:00:55 2014 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Mon Oct 13 13:34:54 2014 +0000
@@ -1870,6 +1870,10 @@
#define AWIN_A31_DMA_IRQ_EN_REG1_PKG_IRQ_EN(n) __BIT((n - 8) * 4 + 1)
#define AWIN_A31_DMA_IRQ_EN_REG1_HLAF_IRQ_EN(n) __BIT((n - 8) * 4 + 0)
+#define AWIN_A31_DMA_IRQ_QUEUE_MASK 0x4444444444444444UL
+#define AWIN_A31_DMA_IRQ_PKG_MASK 0x2222222222222222UL
+#define AWIN_A31_DMA_IRQ_HF_MASK 0x1111111111111111UL
+
#define AWIN_A31_DMA_EN_EN __BIT(0)
#define AWIN_A31_DMA_PAU_PAUSE __BIT(0)
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