Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/dev/ic Add driver for ARM PrimeCell MultiMedia Card Inte...
details: https://anonhg.NetBSD.org/src/rev/6298f6a1b59b
branches: trunk
changeset: 335867:6298f6a1b59b
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Tue Jan 27 16:33:26 2015 +0000
description:
Add driver for ARM PrimeCell MultiMedia Card Interface (PL181). Not tested
with real hardware, only qemu "integratorcp" configuration.
diffstat:
sys/dev/ic/pl181.c | 423 ++++++++++++++++++++++++++++++++++++++++++++++++++
sys/dev/ic/pl181reg.h | 116 +++++++++++++
sys/dev/ic/pl181var.h | 49 +++++
3 files changed, 588 insertions(+), 0 deletions(-)
diffs (truncated from 600 to 300 lines):
diff -r 96da8bb17fdb -r 6298f6a1b59b sys/dev/ic/pl181.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/ic/pl181.c Tue Jan 27 16:33:26 2015 +0000
@@ -0,0 +1,423 @@
+/* $NetBSD: pl181.c,v 1.1 2015/01/27 16:33:26 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: pl181.c,v 1.1 2015/01/27 16:33:26 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+
+#include <dev/sdmmc/sdmmcvar.h>
+#include <dev/sdmmc/sdmmcchip.h>
+#include <dev/sdmmc/sdmmc_ioreg.h>
+
+#include <dev/ic/pl181reg.h>
+#include <dev/ic/pl181var.h>
+
+static int plmmc_host_reset(sdmmc_chipset_handle_t);
+static uint32_t plmmc_host_ocr(sdmmc_chipset_handle_t);
+static int plmmc_host_maxblklen(sdmmc_chipset_handle_t);
+static int plmmc_card_detect(sdmmc_chipset_handle_t);
+static int plmmc_write_protect(sdmmc_chipset_handle_t);
+static int plmmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
+static int plmmc_bus_clock(sdmmc_chipset_handle_t, int);
+static int plmmc_bus_width(sdmmc_chipset_handle_t, int);
+static int plmmc_bus_rod(sdmmc_chipset_handle_t, int);
+static void plmmc_exec_command(sdmmc_chipset_handle_t,
+ struct sdmmc_command *);
+static void plmmc_card_enable_intr(sdmmc_chipset_handle_t, int);
+static void plmmc_card_intr_ack(sdmmc_chipset_handle_t);
+
+static int plmmc_wait_status(struct plmmc_softc *, uint32_t, int);
+static int plmmc_pio_wait(struct plmmc_softc *,
+ struct sdmmc_command *);
+static int plmmc_pio_transfer(struct plmmc_softc *,
+ struct sdmmc_command *);
+
+static struct sdmmc_chip_functions plmmc_chip_functions = {
+ .host_reset = plmmc_host_reset,
+ .host_ocr = plmmc_host_ocr,
+ .host_maxblklen = plmmc_host_maxblklen,
+ .card_detect = plmmc_card_detect,
+ .write_protect = plmmc_write_protect,
+ .bus_power = plmmc_bus_power,
+ .bus_clock = plmmc_bus_clock,
+ .bus_width = plmmc_bus_width,
+ .bus_rod = plmmc_bus_rod,
+ .exec_command = plmmc_exec_command,
+ .card_enable_intr = plmmc_card_enable_intr,
+ .card_intr_ack = plmmc_card_intr_ack,
+};
+
+#define MMCI_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+#define MMCI_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+
+void
+plmmc_init(struct plmmc_softc *sc)
+{
+ struct sdmmcbus_attach_args saa;
+
+ mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
+ cv_init(&sc->sc_intr_cv, "plmmcirq");
+
+#ifdef PLMMC_DEBUG
+ device_printf(sc->sc_dev, "PeriphID %#x %#x %#x %#x\n",
+ MMCI_READ(sc, MMCI_PERIPH_ID0_REG),
+ MMCI_READ(sc, MMCI_PERIPH_ID1_REG),
+ MMCI_READ(sc, MMCI_PERIPH_ID2_REG),
+ MMCI_READ(sc, MMCI_PERIPH_ID3_REG));
+ device_printf(sc->sc_dev, "PCellID %#x %#x %#x %#x\n",
+ MMCI_READ(sc, MMCI_PCELL_ID0_REG),
+ MMCI_READ(sc, MMCI_PCELL_ID1_REG),
+ MMCI_READ(sc, MMCI_PCELL_ID2_REG),
+ MMCI_READ(sc, MMCI_PCELL_ID3_REG));
+#endif
+
+ plmmc_bus_clock(sc, 400);
+ MMCI_WRITE(sc, MMCI_POWER_REG, 0);
+ delay(10000);
+ MMCI_WRITE(sc, MMCI_POWER_REG, MMCI_POWER_CTRL_POWERUP);
+ delay(10000);
+ MMCI_WRITE(sc, MMCI_POWER_REG, MMCI_POWER_CTRL_POWERON);
+ plmmc_host_reset(sc);
+
+ memset(&saa, 0, sizeof(saa));
+ saa.saa_busname = "sdmmc";
+ saa.saa_sct = &plmmc_chip_functions;
+ saa.saa_sch = sc;
+ saa.saa_clkmin = 400;
+ saa.saa_clkmax = sc->sc_clock_freq / 1000;
+ saa.saa_caps = 0;
+
+ sc->sc_sdmmc_dev = config_found(sc->sc_dev, &saa, NULL);
+}
+
+int
+plmmc_intr(void *priv)
+{
+ struct plmmc_softc *sc = priv;
+ uint32_t status;
+
+ mutex_enter(&sc->sc_intr_lock);
+ status = MMCI_READ(sc, MMCI_STATUS_REG);
+#ifdef PLMMC_DEBUG
+ printf("%s: MMCI_STATUS_REG = %#x\n", __func__, status);
+#endif
+ if (!status) {
+ mutex_exit(&sc->sc_intr_lock);
+ return 0;
+ }
+
+ sc->sc_intr_status |= status;
+ cv_broadcast(&sc->sc_intr_cv);
+
+ mutex_exit(&sc->sc_intr_lock);
+
+ return 1;
+}
+
+static int
+plmmc_wait_status(struct plmmc_softc *sc, uint32_t mask, int timeout)
+{
+ int retry, error;
+
+ KASSERT(mutex_owned(&sc->sc_intr_lock));
+
+ if (sc->sc_intr_status & mask)
+ return 0;
+
+ retry = timeout / hz;
+ if (sc->sc_ih == NULL)
+ retry *= 1000;
+
+ while (retry > 0) {
+ if (sc->sc_ih == NULL) {
+ sc->sc_intr_status |= MMCI_READ(sc, MMCI_STATUS_REG);
+ if (sc->sc_intr_status & mask)
+ return 0;
+ delay(10000);
+ } else {
+ error = cv_timedwait(&sc->sc_intr_cv,
+ &sc->sc_intr_lock, hz);
+ if (error && error != EWOULDBLOCK) {
+ device_printf(sc->sc_dev,
+ "cv_timedwait returned %d\n", error);
+ return error;
+ }
+ if (sc->sc_intr_status & mask)
+ return 0;
+ }
+ --retry;
+ }
+
+ device_printf(sc->sc_dev, "%s timeout, MMCI_STATUS_REG = %#x\n",
+ __func__, MMCI_READ(sc, MMCI_STATUS_REG));
+
+ return ETIMEDOUT;
+}
+
+static int
+plmmc_pio_wait(struct plmmc_softc *sc, struct sdmmc_command *cmd)
+{
+ uint32_t bit = (cmd->c_flags & SCF_CMD_READ) ?
+ MMCI_INT_RX_DATA_AVAIL : MMCI_INT_TX_FIFO_EMPTY;
+
+ MMCI_WRITE(sc, MMCI_CLEAR_REG, bit);
+ const int error = plmmc_wait_status(sc,
+ bit | MMCI_INT_DATA_END | MMCI_INT_DATA_BLOCK_END, hz*2);
+ sc->sc_intr_status &= ~bit;
+
+ return error;
+}
+
+static int
+plmmc_pio_transfer(struct plmmc_softc *sc, struct sdmmc_command *cmd)
+{
+ uint32_t *datap = (uint32_t *)cmd->c_data;
+ int i;
+
+ cmd->c_resid = cmd->c_datalen;
+ for (i = 0; i < (cmd->c_datalen >> 2); i++) {
+ if (plmmc_pio_wait(sc, cmd))
+ return ETIMEDOUT;
+ if (cmd->c_flags & SCF_CMD_READ) {
+ datap[i] = MMCI_READ(sc, MMCI_FIFO_REG);
+ } else {
+ MMCI_WRITE(sc, MMCI_FIFO_REG, datap[i]);
+ }
+ cmd->c_resid -= 4;
+ }
+
+ return 0;
+}
+
+static int
+plmmc_host_reset(sdmmc_chipset_handle_t sch)
+{
+ struct plmmc_softc *sc = sch;
+
+ MMCI_WRITE(sc, MMCI_MASK0_REG, 0);
+ MMCI_WRITE(sc, MMCI_MASK1_REG, 0);
+ MMCI_WRITE(sc, MMCI_CLEAR_REG, 0xffffffff);
+
+ return 0;
+}
+
+static uint32_t
+plmmc_host_ocr(sdmmc_chipset_handle_t sch)
+{
+ return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V;
+}
+
+static int
+plmmc_host_maxblklen(sdmmc_chipset_handle_t sch)
+{
+ return 2048;
+}
+
+static int
+plmmc_card_detect(sdmmc_chipset_handle_t sch)
+{
+ return 1;
+}
+
+static int
+plmmc_write_protect(sdmmc_chipset_handle_t sch)
+{
+ return 0;
+}
+
+static int
+plmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
+{
+ return 0;
+}
+
+static int
+plmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
+{
+ struct plmmc_softc *sc = sch;
+ u_int pll_freq, clk_div;
+ uint32_t clock;
+
+ clock = MMCI_CLOCK_PWRSAVE;
+ if (freq) {
+ pll_freq = sc->sc_clock_freq / 1000;
+ clk_div = (howmany(pll_freq, freq) >> 1) - 1;
+ clock |= __SHIFTIN(clk_div, MMCI_CLOCK_CLKDIV);
+ clock |= MMCI_CLOCK_ENABLE;
+ }
+ MMCI_WRITE(sc, MMCI_CLOCK_REG, clock);
+
+ return 0;
+}
+
+static int
+plmmc_bus_width(sdmmc_chipset_handle_t sch, int width)
+{
+ return 0;
+}
+
+static int
+plmmc_bus_rod(sdmmc_chipset_handle_t sch, int on)
+{
+ struct plmmc_softc *sc = sch;
+ uint32_t power;
Home |
Main Index |
Thread Index |
Old Index