[src/trunk]: src/sys/arch/arm According to the Cortex-A5 TRM, the CBAR regist...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0e5eb22528fc
branches:  trunk
changeset: 336031:0e5eb22528fc
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Feb 07 17:14:32 2015 +0000

description:
According to the Cortex-A5 TRM, the CBAR register is not implemented and
always reads as 0x00000000. Add ARM_CBAR option to set this in kernel
config.

diffstat:

 sys/arch/arm/conf/files.arm     |   4 +++-
 sys/arch/arm/cortex/a9_mpsubr.S |  12 +++++++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diffs (53 lines):

diff -r 83ea047b58d2 -r 0e5eb22528fc sys/arch/arm/conf/files.arm
--- a/sys/arch/arm/conf/files.arm       Sat Feb 07 14:37:42 2015 +0000
+++ b/sys/arch/arm/conf/files.arm       Sat Feb 07 17:14:32 2015 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.arm,v 1.129 2014/12/01 08:39:43 matt Exp $
+#      $NetBSD: files.arm,v 1.130 2015/02/07 17:14:32 jmcneill Exp $
 
 # temporary define to allow easy moving to ../arch/arm/arm32
 defflag                                ARM32
@@ -68,6 +68,8 @@
 # use extended small page in compatible MMU mode for ARMv6
 defflag  opt_cpuoptions.h      SHEEVA_L2_CACHE
 defflag  opt_cpuoptions.h      SHEEVA_L2_CACHE_WT: SHEEVA_L2_CACHE
+# override configuration base address register
+defparam opt_cpuoptions.h      ARM_CBAR
 
 # Interrupt implementation header definition.
 defparam opt_arm_intr_impl.h   ARM_INTR_IMPL
diff -r 83ea047b58d2 -r 0e5eb22528fc sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S   Sat Feb 07 14:37:42 2015 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S   Sat Feb 07 17:14:32 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: a9_mpsubr.S,v 1.27 2015/02/07 02:39:56 jmcneill Exp $  */
+/*     $NetBSD: a9_mpsubr.S,v 1.28 2015/02/07 17:14:32 jmcneill Exp $  */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -365,7 +365,12 @@
        // Step 1a, invalidate the all cache tags in all ways on the SCU.
        //
        XPUTC(#65)
+#if defined(ARM_CBAR)
+       movw    r3, #:lower16:ARM_CBAR
+       movt    r3, #:upper16:ARM_CBAR
+#else
        mrc     p15, 4, r3, c15, c0, 0          // read cbar
+#endif
 #ifdef __ARMEB__
        setend  le
 #endif
@@ -419,7 +424,12 @@
        //
        // Step 3, enable the SCU
        //
+#if defined(ARM_CBAR)
+       movw    r3, #:lower16:ARM_CBAR
+       movt    r3, #:upper16:ARM_CBAR
+#else
        mrc     p15, 4, r3, c15, c0, 0          // read cbar
+#endif
 #ifdef __ARMEB__
        setend  le
 #endif