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[src/trunk]: src/sys/arch/sparc64 Make bus_space_barrier inline to avoid unne...
details: https://anonhg.NetBSD.org/src/rev/9a7186571fe6
branches: trunk
changeset: 330577:9a7186571fe6
user: nakayama <nakayama%NetBSD.org@localhost>
date: Mon Jul 14 12:40:38 2014 +0000
description:
Make bus_space_barrier inline to avoid unnecessary argument handling.
diffstat:
sys/arch/sparc64/include/bus_funcs.h | 26 +++++++++++++++++++++++++-
sys/arch/sparc64/sparc64/machdep.c | 25 ++-----------------------
2 files changed, 27 insertions(+), 24 deletions(-)
diffs (86 lines):
diff -r cba50cf58338 -r 9a7186571fe6 sys/arch/sparc64/include/bus_funcs.h
--- a/sys/arch/sparc64/include/bus_funcs.h Mon Jul 14 12:38:00 2014 +0000
+++ b/sys/arch/sparc64/include/bus_funcs.h Mon Jul 14 12:40:38 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bus_funcs.h,v 1.2 2011/07/17 23:29:10 dyoung Exp $ */
+/* $NetBSD: bus_funcs.h,v 1.3 2014/07/14 12:40:38 nakayama Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -125,6 +125,30 @@
#define bus_space_vaddr(t, h) (PHYS_ASI((h)._asi) ? \
NULL : (void *)(vaddr_t)((h)._ptr))
+#define bus_space_barrier(t, h, o, s, f) \
+ sparc_bus_space_barrier((t), (h), (o), (s), (f))
+
+static __inline void
+sparc_bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h,
+ bus_size_t o, bus_size_t s, int f)
+{
+ /*
+ * We have a bit of a problem with the bus_space_barrier()
+ * interface. It defines a read barrier and a write barrier
+ * which really don't map to the 7 different types of memory
+ * barriers in the SPARC v9 instruction set.
+ */
+ if (f == BUS_SPACE_BARRIER_READ)
+ /* A load followed by a load to the same location? */
+ __asm volatile("membar #Lookaside");
+ else if (f == BUS_SPACE_BARRIER_WRITE)
+ /* A store followed by a store? */
+ __asm volatile("membar #StoreStore");
+ else
+ /* A store followed by a load? */
+ __asm volatile("membar #StoreLoad|#MemIssue|#Lookaside");
+}
+
/*
* uintN_t bus_space_read_N(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset);
diff -r cba50cf58338 -r 9a7186571fe6 sys/arch/sparc64/sparc64/machdep.c
--- a/sys/arch/sparc64/sparc64/machdep.c Mon Jul 14 12:38:00 2014 +0000
+++ b/sys/arch/sparc64/sparc64/machdep.c Mon Jul 14 12:40:38 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.277 2014/05/13 19:39:40 palle Exp $ */
+/* $NetBSD: machdep.c,v 1.278 2014/07/14 12:40:38 nakayama Exp $ */
/*-
* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -71,7 +71,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.277 2014/05/13 19:39:40 palle Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.278 2014/07/14 12:40:38 nakayama Exp $");
#include "opt_ddb.h"
#include "opt_multiprocessor.h"
@@ -1611,27 +1611,6 @@
struct extent *io_space = NULL;
-void
-bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h,
- bus_size_t o, bus_size_t s, int f)
-{
- /*
- * We have a bit of a problem with the bus_space_barrier()
- * interface. It defines a read barrier and a write barrier
- * which really don't map to the 7 different types of memory
- * barriers in the SPARC v9 instruction set.
- */
- if (f == BUS_SPACE_BARRIER_READ)
- /* A load followed by a load to the same location? */
- __asm volatile("membar #Lookaside");
- else if (f == BUS_SPACE_BARRIER_WRITE)
- /* A store followed by a store? */
- __asm volatile("membar #StoreStore");
- else
- /* A store followed by a load? */
- __asm volatile("membar #StoreLoad|#MemIssue|#Lookaside");
-}
-
int
bus_space_alloc(bus_space_tag_t t, bus_addr_t rs, bus_addr_t re, bus_size_t s,
bus_size_t a, bus_size_t b, int f, bus_addr_t *ap,
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