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[src/trunk]: src/sys/arch/sparc64 sun4v: Introduce SET_MMU_CONTEXTID macro fo...
details: https://anonhg.NetBSD.org/src/rev/7e63c74f8ef3
branches: trunk
changeset: 330639:7e63c74f8ef3
user: palle <palle%NetBSD.org@localhost>
date: Wed Jul 16 19:53:18 2014 +0000
description:
sun4v: Introduce SET_MMU_CONTEXTID macro for setting the mmu context id on both sun4u and sun4v
diffstat:
sys/arch/sparc64/include/ctlreg.h | 4 +++-
sys/arch/sparc64/sparc64/locore.s | 34 +++++++++++++++++++++++++++-------
2 files changed, 30 insertions(+), 8 deletions(-)
diffs (93 lines):
diff -r d61259eef7d1 -r 7e63c74f8ef3 sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Wed Jul 16 19:35:23 2014 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Wed Jul 16 19:53:18 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ctlreg.h,v 1.60 2013/12/16 20:17:35 palle Exp $ */
+/* $NetBSD: ctlreg.h,v 1.61 2014/07/16 19:53:18 palle Exp $ */
/*
* Copyright (c) 1996-2002 Eduardo Horvath
@@ -55,6 +55,8 @@
#define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */
#define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */
+#define ASI_MMU 0x21 /* [4v] MMU context control - both IMMU and DMMU */
+
#define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */
#define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */
diff -r d61259eef7d1 -r 7e63c74f8ef3 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Wed Jul 16 19:35:23 2014 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Wed Jul 16 19:53:18 2014 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.363 2014/07/13 22:32:49 palle Exp $ */
+/* $NetBSD: locore.s,v 1.364 2014/07/16 19:53:18 palle Exp $ */
/*
* Copyright (c) 2006-2010 Matthew R. Green
@@ -101,7 +101,7 @@
#include "ksyms.h"
/* Misc. macros */
-
+
.macro GET_MAXCWP reg
#ifdef SUN4V
sethi %hi(cputyp), \reg
@@ -120,7 +120,27 @@
3:
.endm
-
+
+ .macro SET_MMU_CONTEXTID ctxid,ctx,scratch
+#ifdef SUN4V
+ sethi %hi(cputyp), \scratch
+ ld [\scratch + %lo(cputyp)], \scratch
+ cmp \scratch, CPU_SUN4V
+ bne,pt %icc, 2f
+ nop
+ /* sun4v */
+ stxa \ctxid, [\ctx] ASI_MMU;
+ ba 3f
+ nop
+2:
+#endif
+ /* sun4u */
+ stxa \ctxid, [\ctx] ASI_DMMU;
+3:
+
+ .endm
+
+
#ifdef SUN4V
/* Misc. sun4v macros */
@@ -1362,13 +1382,13 @@
\
wrpr %g0, %g5, %otherwin; \
\
- sethi %hi(KERNBASE), %g5; \
mov CTX_PRIMARY, %g7; \
\
wrpr %g0, WSTATE_KERN, %wstate; /* Enable kernel mode window traps -- now we can trap again */ \
\
- stxa %g0, [%g7] ASI_DMMU; /* Switch MMU to kernel primary context */ \
+ SET_MMU_CONTEXTID %g0, %g7, %g5; /* Switch MMU to kernel primary context */ \
\
+ sethi %hi(KERNBASE), %g5; \
flush %g5; /* Some convenient address that won't trap */ \
1:
@@ -1463,9 +1483,9 @@
wrpr %g0, 0, %canrestore; \
mov CTX_PRIMARY, %g7; \
wrpr %g0, %g5, %otherwin; \
+ wrpr %g0, WSTATE_KERN, %wstate; /* Enable kernel mode window traps -- now we can trap again */ \
+ SET_MMU_CONTEXTID %g0, %g7, %g5; /* Switch MMU to kernel primary context */ \
sethi %hi(KERNBASE), %g5; \
- wrpr %g0, WSTATE_KERN, %wstate; /* Enable kernel mode window traps -- now we can trap again */ \
- stxa %g0, [%g7] ASI_DMMU; /* Switch MMU to kernel primary context */ \
flush %g5; /* Some convenient address that won't trap */ \
1:
#endif /* _LP64 */
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