[src/trunk]: src/sys/arch/arm/cortex allow arml2cc to be used on Cortex-A5 if...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f4ac8dfd24c3
branches:  trunk
changeset: 336386:f4ac8dfd24c3
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Fri Feb 27 20:40:09 2015 +0000

description:
allow arml2cc to be used on Cortex-A5 if the "offset" property is specified

diffstat:

 sys/arch/arm/cortex/armperiph.c |   3 ++-
 sys/arch/arm/cortex/pl310.c     |  18 ++++++++++++++----
 2 files changed, 16 insertions(+), 5 deletions(-)

diffs (74 lines):

diff -r c8b0ef3f7f0a -r f4ac8dfd24c3 sys/arch/arm/cortex/armperiph.c
--- a/sys/arch/arm/cortex/armperiph.c   Fri Feb 27 19:57:10 2015 +0000
+++ b/sys/arch/arm/cortex/armperiph.c   Fri Feb 27 20:40:09 2015 +0000
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.6 2015/02/27 18:43:28 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: armperiph.c,v 1.7 2015/02/27 20:40:09 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -64,6 +64,7 @@
        { "armgic", 0x1000, 0x0100 },
        { "a9tmr",  0x0200, 0 },
        { "a9wdt",   0x0600, 0 },
+       { "arml2cc", 0, 0 },    /* external; needs "offset" property */
        { "", 0, 0 },
 };
 #endif
diff -r c8b0ef3f7f0a -r f4ac8dfd24c3 sys/arch/arm/cortex/pl310.c
--- a/sys/arch/arm/cortex/pl310.c       Fri Feb 27 19:57:10 2015 +0000
+++ b/sys/arch/arm/cortex/pl310.c       Fri Feb 27 20:40:09 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pl310.c,v 1.16 2014/12/01 22:39:06 matt Exp $  */
+/*     $NetBSD: pl310.c,v 1.17 2015/02/27 20:40:09 jmcneill Exp $      */
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.16 2014/12/01 22:39:06 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.17 2015/02/27 20:40:09 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -99,7 +99,8 @@
        if (arml2cc_sc)
                return 0;
 
-       if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid))
+       if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) &&
+           !CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
                return 0;
 
        if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0)
@@ -138,7 +139,17 @@
        prop_dictionary_t dict = device_properties(self);
        uint32_t off;
 
+       aprint_naive("\n");
+
        if (!prop_dictionary_get_uint32(dict, "offset", &off)) {
+               if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) {
+                       /*
+                        * PL310 on Cortex-A5 is external to PERIPHBASE, so
+                        * "offset" property is required.
+                        */
+                       aprint_normal(": not configured\n");
+                       return;
+               }
                off = L2CC_BASE;
        }
 
@@ -172,7 +183,6 @@
 
        const bool enabled_p = arml2cc_read_4(sc, L2C_CTL) != 0;
 
-       aprint_naive("\n");
        aprint_normal(": ARM PL310%s L2 Cache Controller%s\n",
            revstr, enabled_p ? "" : " (disabled)");