[src/trunk]: src/sys/arch/arm/arm Trailing whitespace.

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/381e2d72b576
branches:  trunk
changeset: 331065:381e2d72b576
user:      skrll <skrll%NetBSD.org@localhost>
date:      Wed Jul 30 07:11:57 2014 +0000

description:
Trailing whitespace.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_arm11x6.S |  44 +++++++++++++++++-----------------
 1 files changed, 22 insertions(+), 22 deletions(-)

diffs (96 lines):

diff -r cd1595e6c991 -r 381e2d72b576 sys/arch/arm/arm/cpufunc_asm_arm11x6.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm11x6.S    Wed Jul 30 06:53:53 2014 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm11x6.S    Wed Jul 30 07:11:57 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm11x6.S,v 1.4 2014/03/30 01:15:03 matt Exp $     */
+/*     $NetBSD: cpufunc_asm_arm11x6.S,v 1.5 2014/07/30 07:11:57 skrll Exp $    */
 
 /*
  * Copyright (c) 2007 Microsoft
@@ -63,7 +63,7 @@
 #include <machine/asm.h>
 #include <arm/locore.h>
 
-RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.4 2014/03/30 01:15:03 matt Exp $")
+RCSID("$NetBSD: cpufunc_asm_arm11x6.S,v 1.5 2014/07/30 07:11:57 skrll Exp $")
 
 #if 0
 #define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -74,7 +74,7 @@
  *
  *    Erratum 411920 in ARM1136 (fixed in r1p4)
  *    Erratum 415045 in ARM1176 (fixed in r0p5?)
- * 
+ *
  *     - value of arg 'reg' Should Be Zero
  */
 #define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -143,20 +143,20 @@
        /* Erratum ARM1176 371367 */
        mrs     r2, cpsr                /* save the CPSR */
        cpsid   ifa                     /* disable interrupts (irq,fiq,abort) */
-       mov     r3, #0 
+       mov     r3, #0
        mcr     p15, 0, r3, c13, c0, 0  /* write FCSE (uTLB invalidate) */
        mcr     p15, 0, r3, c7, c5, 4   /* flush prefetch buffer */
-       add     r3, pc, #0x24 
+       add     r3, pc, #0x24
        mcr     p15, 0, r3, c7, c13, 1  /* prefetch I-cache line */
        mcrr    p15, 0, r1, r0, c5      /* invalidate I-cache range */
        msr     cpsr_cx, r2             /* local_irq_restore */
-       nop 
-       nop 
-       nop 
-       nop 
-       nop 
-       nop 
-       nop 
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
 
        mcrr    p15, 0, r1, r0, c12     /* clean and invalidate D cache range */ /* XXXNH */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
@@ -170,20 +170,20 @@
        /* Erratum ARM1176 371367 */
        mrs     r2, cpsr                /* save the CPSR */
        cpsid   ifa                     /* disable interrupts (irq,fiq,abort) */
-       mov     r3, #0 
+       mov     r3, #0
        mcr     p15, 0, r3, c13, c0, 0  /* write FCSE (uTLB invalidate) */
        mcr     p15, 0, r3, c7, c5, 4   /* flush prefetch buffer */
-       add     r3, pc, #0x24 
+       add     r3, pc, #0x24
        mcr     p15, 0, r3, c7, c13, 1  /* prefetch I-cache line */
        mcrr    p15, 0, r1, r0, c5      /* invalidate I-cache range */
        msr     cpsr_cx, r2             /* local_irq_restore */
-       nop 
-       nop 
-       nop 
-       nop 
-       nop 
-       nop 
-       nop 
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
+       nop
 
        mcrr    p15, 0, r1, r0, c14     /* clean and invalidate D cache range */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
@@ -192,7 +192,7 @@
 
 /*
  * Preload the cache before issuing the WFI by conditionally disabling the
- * mcr intstructions the first time around the loop. Ensure the function is 
+ * mcr intstructions the first time around the loop. Ensure the function is
  * cacheline aligned.
  */
        .arch   armv6