[src/trunk]: src/sys/arch/x86/x86 Modify p3_get_bus_clock():

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/15df81046f5f
branches:  trunk
changeset: 330938:15df81046f5f
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Jul 25 14:34:22 2014 +0000

description:
Modify p3_get_bus_clock():
- Intel SDM says 06_17H is the same as 06_0fH. Same as OpenBSD.
- Add some Silvermont models.
- For Slivermont architecture, 0x011 is not 166.67MHz but 116.67MHz.
- Print model name not in decimal but in hexadecimal
- Cleanup code.

diffstat:

 sys/arch/x86/x86/intel_busclock.c |  26 +++++++++++---------------
 1 files changed, 11 insertions(+), 15 deletions(-)

diffs (77 lines):

diff -r 76de532a97b4 -r 15df81046f5f sys/arch/x86/x86/intel_busclock.c
--- a/sys/arch/x86/x86/intel_busclock.c Fri Jul 25 14:18:49 2014 +0000
+++ b/sys/arch/x86/x86/intel_busclock.c Fri Jul 25 14:34:22 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: intel_busclock.c,v 1.18 2013/11/17 19:22:06 martin Exp $       */
+/*     $NetBSD: intel_busclock.c,v 1.19 2014/07/25 14:34:22 msaitoh Exp $      */
 
 /*-
  * Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_busclock.c,v 1.18 2013/11/17 19:22:06 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_busclock.c,v 1.19 2014/07/25 14:34:22 msaitoh Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -144,18 +144,8 @@
                }
                break;
        case 0xe: /* Core Duo/Solo */
-               /*
-                * XXX (See also case 0xc)
-                * Newer CPUs will GP when attemping to access MSR_FSB_FREQ.
-                * In the long-term, use ACPI instead of all this.
-                */
-               if (rdmsr_safe(MSR_FSB_FREQ, &msr) == EFAULT) {
-                       aprint_debug_dev(ci->ci_dev,
-                           "unable to determine bus speed");
-                       goto print_msr;
-               }
-               /* FALLTHROUGH */
        case 0xf: /* Core Xeon */
+       case 0x17: /* Xeon [35]000, Core 2 Quad [89]00 */
                if (rdmsr_safe(MSR_FSB_FREQ, &msr) == EFAULT) {
                        aprint_debug_dev(ci->ci_dev,
                            "unable to determine bus speed");
@@ -181,6 +171,9 @@
                case 4:
                        bus_clock = 33333;
                        break;
+               case 6:
+                       bus_clock = 40000;
+                       break;
                default:
                        aprint_debug("%s: unknown Core FSB_FREQ value %d",
                            device_xname(ci->ci_dev), bus);
@@ -247,7 +240,10 @@
                }
                break;
        case 0x37: /* Silvermont */
+       case 0x4a:
        case 0x4d:
+       case 0x5a:
+       case 0x5d:
                if (rdmsr_safe(MSR_FSB_FREQ, &msr) == EFAULT) {
                        aprint_debug_dev(ci->ci_dev,
                            "unable to determine bus speed");
@@ -268,7 +264,7 @@
                        bus_clock = 13333;
                        break;
                case 3:
-                       bus_clock = 16667;
+                       bus_clock = 11667;
                        break;
                default:
                        aprint_debug("%s: unknown Silvermont FSB_FREQ value %d",
@@ -277,7 +273,7 @@
                }
                break;
        default:
-               aprint_debug("%s: unknown i686 model %d, can't get bus clock",
+               aprint_debug("%s: unknown i686 model %02x, can't get bus clock",
                    device_xname(ci->ci_dev),
                    CPUID_TO_MODEL(ci->ci_signature));
 print_msr: