[src/trunk]: src/sys/arch/arm/include/arm32 Trailing whitespace

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6abfcd8f9a07
branches:  trunk
changeset: 331099:6abfcd8f9a07
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Jul 31 08:04:57 2014 +0000

description:
Trailing whitespace

diffstat:

 sys/arch/arm/include/arm32/pmap.h |  18 +++++++++---------
 sys/arch/arm/include/arm32/pte.h  |   6 +++---
 2 files changed, 12 insertions(+), 12 deletions(-)

diffs (92 lines):

diff -r 0a90c731216b -r 6abfcd8f9a07 sys/arch/arm/include/arm32/pmap.h
--- a/sys/arch/arm/include/arm32/pmap.h Thu Jul 31 07:14:42 2014 +0000
+++ b/sys/arch/arm/include/arm32/pmap.h Thu Jul 31 08:04:57 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.h,v 1.134 2014/07/27 21:31:34 skrll Exp $ */
+/*     $NetBSD: pmap.h,v 1.135 2014/07/31 08:04:57 skrll Exp $ */
 
 /*
  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -98,14 +98,14 @@
 #include <uvm/pmap/tlb.h>
 #include <uvm/pmap/pmap_tlb.h>
 
-/* 
+/*
  * If we have an EXTENDED MMU and the address space is split evenly between
  * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for
  * user and kernel address spaces.
- */      
+ */
 #if (KERNEL_BASE & 0x80000000) == 0
 #error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000
-#endif  
+#endif
 #endif  /* ARM_MMU_EXTENDED */
 
 /*
@@ -401,7 +401,7 @@
 void   pmap_devmap_register(const struct pmap_devmap *);
 
 /*
- * Special page zero routine for use by the idle loop (no cache cleans). 
+ * Special page zero routine for use by the idle loop (no cache cleans).
  */
 bool   pmap_pageidlezero(paddr_t);
 #define PMAP_PAGEIDLEZERO(pa)  pmap_pageidlezero((pa))
@@ -432,7 +432,7 @@
 #endif
 
 /*
- * Useful macros and constants 
+ * Useful macros and constants
  */
 
 /* Virtual address to page table entry */
@@ -481,7 +481,7 @@
  * we need to do PTE syncs.  If only SA-1 is configured, then evaluate
  * this at compile time.
  */
-#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1) 
+#if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1)
 #define        PMAP_INCLUDE_PTE_SYNC
 #if (ARM_MMU_V6 > 0)
 #define        PMAP_NEEDS_PTE_SYNC     1
@@ -588,7 +588,7 @@
        for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
                ptep[k] = 0;
        }
-}       
+}
 
 /* L1 and L2 page table macros */
 #define pmap_pde_v(pde)                l1pte_valid(*(pde))
@@ -1091,7 +1091,7 @@
 #define        VM_MDPAGE_PVH_ATTRS_INIT(pg) \
        (pg)->mdpage.pvh_attrs = 0
 #endif
- 
+
 #define        VM_MDPAGE_INIT(pg)                                              \
 do {                                                                   \
        SLIST_INIT(&(pg)->mdpage.pvh_list);                             \
diff -r 0a90c731216b -r 6abfcd8f9a07 sys/arch/arm/include/arm32/pte.h
--- a/sys/arch/arm/include/arm32/pte.h  Thu Jul 31 07:14:42 2014 +0000
+++ b/sys/arch/arm/include/arm32/pte.h  Thu Jul 31 08:04:57 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pte.h,v 1.15 2014/02/26 01:53:23 matt Exp $    */
+/*     $NetBSD: pte.h,v 1.16 2014/07/31 08:04:57 skrll Exp $   */
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -326,8 +326,8 @@
  *          (non-cacheable for MPCore)
  *    1 1   Write back, no write alloc, buffered
  *          (write back, write alloc for MPCore)
- *    
- *    AA    external cache 
+ *
+ *    AA    external cache
  *    0 0   Non-cacheable non-buffered
  *    0 1   Write back, write alloc, buffered
  *    1 0   Write through, no write alloc, buffered