[src/trunk]: src/sys/arch/arm/arm32 Fix for PR/49107.

[matt <matt%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/42ddb42e350a
branches:  trunk
changeset: 331509:42ddb42e350a
user:      matt <matt%NetBSD.org@localhost>
date:      Wed Aug 13 05:56:03 2014 +0000

description:
Fix for PR/49107.
Make sure pmap_copy_page_xscale clears the ptes afters its done with them.

diffstat:

 sys/arch/arm/arm32/pmap.c |  24 ++++++++++++++++--------
 1 files changed, 16 insertions(+), 8 deletions(-)

diffs (52 lines):

diff -r b4858c63f3fc -r 42ddb42e350a sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Wed Aug 13 00:03:00 2014 +0000
+++ b/sys/arch/arm/arm32/pmap.c Wed Aug 13 05:56:03 2014 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.295 2014/07/25 15:09:43 matt Exp $  */
+/*     $NetBSD: pmap.c,v 1.296 2014/08/13 05:56:03 matt Exp $  */
 
 /*
  * Copyright 2003 Wasabi Systems, Inc.
@@ -216,7 +216,7 @@
 #include <arm/locore.h>
 //#include <arm/arm32/katelib.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.295 2014/07/25 15:09:43 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.296 2014/08/13 05:56:03 matt Exp $");
 
 //#define PMAP_DEBUG
 #ifdef PMAP_DEBUG
@@ -5518,19 +5518,27 @@
         * the cache for the appropriate page. Invalidate the TLB
         * as required.
         */
-       *csrc_pte = L2_S_PROTO | src |
-           L2_S_PROT(PTE_KERNEL, VM_PROT_READ) |
-           L2_C | L2_XS_T_TEX(TEX_XSCALE_X);   /* mini-data */
+       const pt_entry_t nsrc_pte = L2_S_PROTO | src
+           | L2_S_PROT(PTE_KERNEL, VM_PROT_READ)
+           | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */
+       l2pte_set(csrc_pte, nsrc_pte, 0);
        PTE_SYNC(csrc_pte);
-       *cdst_pte = L2_S_PROTO | dst |
-           L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
-           L2_C | L2_XS_T_TEX(TEX_XSCALE_X);   /* mini-data */
+
+       const pt_entry_t ndst_pte = L2_S_PROTO | dst
+           | L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE)
+           | L2_C | L2_XS_T_TEX(TEX_XSCALE_X); /* mini-data */
+       l2pte_set(cdst_pte, ndst_pte, 0);
        PTE_SYNC(cdst_pte);
+
        cpu_tlb_flushD_SE(csrcp);
        cpu_tlb_flushD_SE(cdstp);
        cpu_cpwait();
        bcopy_page(csrcp, cdstp);
        xscale_cache_clean_minidata();
+       l2pte_reset(csrc_pte);
+       l2pte_reset(cdst_pte);
+       PTE_SYNC(csrc_pte);
+       PTE_SYNC(cdst_pte);
 }
 #endif /* ARM_MMU_XSCALE == 1 */