[src/trunk]: src/sys/arch/sparc64 sun4v: Implement handling of cpu_mondo trap...

[palle <palle%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/acc31ca825e8
branches:  trunk
changeset: 337083:acc31ca825e8
user:      palle <palle%NetBSD.org@localhost>
date:      Wed Apr 01 18:38:30 2015 +0000

description:
sun4v: Implement handling of cpu_mondo trap - from OpenBSD - tested using the Legion simulator

diffstat:

 sys/arch/sparc64/include/ctlreg.h    |   3 ++-
 sys/arch/sparc64/include/trap.h      |   3 ++-
 sys/arch/sparc64/sparc64/genassym.cf |   3 ++-
 sys/arch/sparc64/sparc64/locore.s    |  32 ++++++++++++++++++++++++++++++--
 4 files changed, 36 insertions(+), 5 deletions(-)

diffs (104 lines):

diff -r e3b3f5ed7534 -r acc31ca825e8 sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Wed Apr 01 15:45:00 2015 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Wed Apr 01 18:38:30 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ctlreg.h,v 1.61 2014/07/16 19:53:18 palle Exp $ */
+/*     $NetBSD: ctlreg.h,v 1.62 2015/04/01 18:38:30 palle Exp $ */
 
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath
@@ -58,6 +58,7 @@
 #define ASI_MMU                                0x21    /* [4v] MMU context control - both IMMU and DMMU */
 
 #define        ASI_NUCLEUS_QUAD_LDD            0x24    /* [4u] use w/LDDA to load 128-bit item */
+#define        ASI_QUEUE                       0x25    /* [4v] interrupt queue registers */
 #define        ASI_NUCLEUS_QUAD_LDD_LITTLE     0x2c    /* [4u] use w/LDDA to load 128-bit item, little endian */
 
 #define        ASI_FLUSH_D_PAGE_PRIMARY        0x38    /* [4u] flush D-cache page using primary context */
diff -r e3b3f5ed7534 -r acc31ca825e8 sys/arch/sparc64/include/trap.h
--- a/sys/arch/sparc64/include/trap.h   Wed Apr 01 15:45:00 2015 +0000
+++ b/sys/arch/sparc64/include/trap.h   Wed Apr 01 18:38:30 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: trap.h,v 1.10 2014/06/08 17:33:24 palle Exp $ */
+/*     $NetBSD: trap.h,v 1.11 2015/04/01 18:38:30 palle Exp $ */
 
 /*
  * Copyright (c) 1996-1999 Eduardo Horvath
@@ -96,6 +96,7 @@
 #define T_FAST_ECC_ERROR 0x070 /* (2) fast ECC error [USIII] */
 #define T_DC_PAR_ERR   0x071   /* (2) dcache parity error [USIII] */
 #define T_IC_PAR_ERR   0x072   /* (2) icache parity error [USIII] */
+#define T_CPU_MONDO    0x07c   /* cpu mondo [SUN4V] */
 #define T_SPILL_N_NORM 0x080   /* (9) spill (n=0..7) normal */
 /*     through         0x09f      unused */
 #define T_SPILL_N_OTHER        0x0a0   /* (9) spill (n=0..7) other */
diff -r e3b3f5ed7534 -r acc31ca825e8 sys/arch/sparc64/sparc64/genassym.cf
--- a/sys/arch/sparc64/sparc64/genassym.cf      Wed Apr 01 15:45:00 2015 +0000
+++ b/sys/arch/sparc64/sparc64/genassym.cf      Wed Apr 01 18:38:30 2015 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: genassym.cf,v 1.75 2014/09/24 18:32:10 palle Exp $
+#      $NetBSD: genassym.cf,v 1.76 2015/04/01 18:38:30 palle Exp $
 
 #
 # Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -169,6 +169,7 @@
 define CI_TSB_IMMU     offsetof(struct cpu_info, ci_tsb_immu)
 define CI_MMFSA        offsetof(struct cpu_info, ci_mmfsa)
 define CI_TSB_DESC     offsetof(struct cpu_info, ci_tsb_desc)
+define CI_CPUMQ        offsetof(struct cpu_info, ci_cpumq)
 ifdef MULTIPROCESSOR
 define CI_IPIEVC       offsetof(struct cpu_info, ci_ipi_evcnt[0].ev_count)
 endif
diff -r e3b3f5ed7534 -r acc31ca825e8 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Wed Apr 01 15:45:00 2015 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Wed Apr 01 18:38:30 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.382 2015/03/04 11:32:31 palle Exp $       */
+/*     $NetBSD: locore.s,v 1.383 2015/04/01 18:38:30 palle Exp $       */
 
 /*
  * Copyright (c) 2006-2010 Matthew R. Green
@@ -1040,7 +1040,9 @@
        HARDINT4V(13)                                           ! 0x04d = level 13 interrupt
        HARDINT4V(14)                                           ! 0x04e = level 14 interrupt
        HARDINT4V(15)                                           ! 0x04f = level 15 interrupt
-       sun4v_trap_entry 48                                     ! 0x050-0x07f
+       sun4v_trap_entry 44                                     ! 0x050-0x07b
+       VTRAP(T_CPU_MONDO, sun4v_cpu_mondo)                     ! 0x07c = cpu mondo
+       sun4v_trap_entry 3                                      ! 0x07d-0x07f
        SPILL64(uspill8_sun4vt0,ASI_AIUS)                       ! 0x080 spill_0_normal -- used to save user windows in user mode
        SPILL32(uspill4_sun4vt0,ASI_AIUS)                       ! 0x084 spill_1_normal
        SPILLBOTH(uspill8_sun4vt0,uspill4_sun4vt0,ASI_AIUS)     ! 0x088 spill_2_normal
@@ -3558,6 +3560,32 @@
        ba,a    ret_from_intr_vector
         nop                            ! XXX spitfire bug?
 
+sun4v_cpu_mondo:
+       mov     0x3c0, %g1                       ! CPU Mondo Queue Head
+       ldxa    [%g1] ASI_QUEUE, %g2             ! fetch index value for head
+       set     CPUINFO_VA, %g3
+       LDPTR   [%g3 + CI_PADDR], %g3
+       add     %g3, CI_CPUMQ, %g3      
+       ldxa    [%g3] ASI_PHYS_CACHED, %g3       ! fetch head element
+       ldxa    [%g3 + %g2] ASI_PHYS_CACHED, %g4 ! fetch func 
+       add     %g2, 8, %g5
+       ldxa    [%g3 + %g5] ASI_PHYS_CACHED, %g5 ! fetch arg1
+       add     %g2, 16, %g6
+       ldxa    [%g3 + %g6] ASI_PHYS_CACHED, %g6 ! fetch arg2
+       add     %g2, 64, %g2                     ! point to next element in queue
+       and     %g2, 0x7ff, %g2                  ! modulo queue size 2048 (32*64)
+       stxa    %g2, [%g1] ASI_QUEUE             ! update head index
+       membar  #Sync
+
+       mov     %g4, %g2
+       mov     %g5, %g3
+       mov     %g6, %g5
+       jmpl    %g2, %g0
+        nop                    ! No store here!
+       retry
+       NOTREACHED
+
+       
 /*
  * Ultra1 and Ultra2 CPUs use soft interrupts for everything.  What we do
  * on a soft interrupt, is we should check which bits in SOFTINT(%asr22)