[src/trunk]: src/sys/arch/arm/marvell add L2 cache write eviction buffer sync...

[hsuenaga <hsuenaga%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/5ea0bac6dc92
branches:  trunk
changeset: 337465:5ea0bac6dc92
user:      hsuenaga <hsuenaga%NetBSD.org@localhost>
date:      Wed Apr 15 12:11:31 2015 +0000

description:
add L2 cache write eviction buffer sync barrier

diffstat:

 sys/arch/arm/marvell/armadaxp.c |  8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diffs (50 lines):

diff -r 1b0172ca6b55 -r 5ea0bac6dc92 sys/arch/arm/marvell/armadaxp.c
--- a/sys/arch/arm/marvell/armadaxp.c   Wed Apr 15 10:52:18 2015 +0000
+++ b/sys/arch/arm/marvell/armadaxp.c   Wed Apr 15 12:11:31 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armadaxp.c,v 1.9 2015/04/15 10:40:36 hsuenaga Exp $    */
+/*     $NetBSD: armadaxp.c,v 1.10 2015/04/15 12:11:31 hsuenaga Exp $   */
 /*******************************************************************************
 Copyright (C) Marvell International Ltd. and its affiliates
 
@@ -37,7 +37,7 @@
 *******************************************************************************/
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.9 2015/04/15 10:40:36 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: armadaxp.c,v 1.10 2015/04/15 12:11:31 hsuenaga Exp $");
 
 #define _INTR_PRIVATE
 
@@ -485,6 +485,7 @@
 armadaxp_sdcache_wb_all(void)
 {
        L2_WRITE(ARMADAXP_L2_WB_WAY, L2_ALL_WAYS);
+       L2_WRITE(ARMADAXP_L2_SYNC, 0);
        __asm__ __volatile__("dsb");
 }
 
@@ -492,6 +493,7 @@
 armadaxp_sdcache_wbinv_all(void)
 {
        L2_WRITE(ARMADAXP_L2_WBINV_WAY, L2_ALL_WAYS);
+       L2_WRITE(ARMADAXP_L2_SYNC, 0);
        __asm__ __volatile__("dsb");
 }
 
@@ -515,6 +517,7 @@
        pa_end = (pa_base + sz) & ~0x1f;
        L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
        L2_WRITE(ARMADAXP_L2_WB_RANGE, pa_end);
+       L2_WRITE(ARMADAXP_L2_SYNC, 0);
        __asm__ __volatile__("dsb");
 }
 
@@ -527,6 +530,7 @@
        pa_end = (pa_base + sz) & ~0x1f;
        L2_WRITE(ARMADAXP_L2_RANGE_BASE, pa_base);
        L2_WRITE(ARMADAXP_L2_WBINV_RANGE, pa_end);
+       L2_WRITE(ARMADAXP_L2_SYNC, 0);
        __asm__ __volatile__("dsb");
 }