[src/trunk]: src/sys/arch/arm/allwinner fix attachment of non-console UARTs a...

[tnn <tnn%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/4ce20e899039
branches:  trunk
changeset: 339766:4ce20e899039
user:      tnn <tnn%NetBSD.org@localhost>
date:      Sat Aug 08 23:30:16 2015 +0000

description:
fix attachment of non-console UARTs and ensure the UART clock is running

diffstat:

 sys/arch/arm/allwinner/awin_com.c |  25 +++++++++++++++++++++++--
 sys/arch/arm/allwinner/awin_reg.h |  23 ++++++++++++++++++++++-
 2 files changed, 45 insertions(+), 3 deletions(-)

diffs (93 lines):

diff -r 2fa8cc0c14d1 -r 4ce20e899039 sys/arch/arm/allwinner/awin_com.c
--- a/sys/arch/arm/allwinner/awin_com.c Sat Aug 08 23:06:36 2015 +0000
+++ b/sys/arch/arm/allwinner/awin_com.c Sat Aug 08 23:30:16 2015 +0000
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: awin_com.c,v 1.9 2014/12/07 12:44:24 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_com.c,v 1.10 2015/08/08 23:30:16 tnn Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -130,7 +130,28 @@
        awin_gpio_pinset_acquire(pinset);
 
        bus_space_subregion(iot, aio->aio_core_bsh,
-           loc->loc_offset, loc->loc_size, &bsh);
+           loc->loc_offset / 4, loc->loc_size, &bsh);
+
+       /*
+        * Clock gating, soft reset
+        */
+       if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+               awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+                   AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_REG,
+                   AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART0 << loc->loc_port, 0);
+               awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+                   AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_REG,
+                   AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART0 << loc->loc_port, 0);
+       } else {
+               awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+                  AWIN_APB1_GATING_REG,
+                  AWIN_APB_GATING1_UART0 << loc->loc_port, 0);
+               if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+                       awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+                           AWIN_A31_APB2_RESET_REG,
+                           AWIN_A31_APB2_RESET_UART0_RST << loc->loc_port, 0);
+               }
+       }
 
        const int rv = comprobe1(iot, bsh);
 
diff -r 2fa8cc0c14d1 -r 4ce20e899039 sys/arch/arm/allwinner/awin_reg.h
--- a/sys/arch/arm/allwinner/awin_reg.h Sat Aug 08 23:06:36 2015 +0000
+++ b/sys/arch/arm/allwinner/awin_reg.h Sat Aug 08 23:30:16 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: awin_reg.h,v 1.78 2015/06/03 12:22:41 skrll Exp $ */
+/* $NetBSD: awin_reg.h,v 1.79 2015/08/08 23:30:16 tnn Exp $ */
 
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -2416,6 +2416,13 @@
 #define AWIN_A31_APB1_RESET_DIGITAL_MIC_RST    __BIT(4)
 #define AWIN_A31_APB1_RESET_CODEC_RST          __BIT(0)
 
+#define AWIN_A31_APB2_RESET_UART5_RST          __BIT(21)
+#define AWIN_A31_APB2_RESET_UART4_RST          __BIT(20)
+#define AWIN_A31_APB2_RESET_UART3_RST          __BIT(19)
+#define AWIN_A31_APB2_RESET_UART2_RST          __BIT(18)
+#define AWIN_A31_APB2_RESET_UART1_RST          __BIT(17)
+#define AWIN_A31_APB2_RESET_UART0_RST          __BIT(16)
+
 #define AWIN_A31_APB2_RESET_TWI3_RST           __BIT(3)
 #define AWIN_A31_APB2_RESET_TWI2_RST           __BIT(2)
 #define AWIN_A31_APB2_RESET_TWI1_RST           __BIT(1)
@@ -2786,6 +2793,13 @@
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_GMAC __BIT(17)
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_USB_HOST __BIT(1)
 
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART5        __BIT(21)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART4        __BIT(20)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART3        __BIT(19)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART2        __BIT(18)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART1        __BIT(17)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART0        __BIT(16)
+
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI4 __BIT(4)
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI2 __BIT(3)
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI3 __BIT(2)
@@ -2798,6 +2812,13 @@
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_GMAC   __BIT(17)
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_USB_DRD        __BIT(1)
 
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART5  __BIT(21)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART4  __BIT(20)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART3  __BIT(19)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART2  __BIT(18)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART1  __BIT(17)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART0  __BIT(16)
+
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI4   __BIT(4)
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI3   __BIT(3)
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI2   __BIT(2)