[src/trunk]: src/sys/arch/mips/ingenic - sprinkle volatile

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2006e99792f2
branches:  trunk
changeset: 339740:2006e99792f2
user:      macallan <macallan%NetBSD.org@localhost>
date:      Fri Aug 07 17:37:54 2015 +0000

description:
- sprinkle volatile
- add RNG registers
- fix some comments

diffstat:

 sys/arch/mips/ingenic/ingenic_regs.h |  19 ++++++++++++++-----
 1 files changed, 14 insertions(+), 5 deletions(-)

diffs (54 lines):

diff -r c83645d67449 -r 2006e99792f2 sys/arch/mips/ingenic/ingenic_regs.h
--- a/sys/arch/mips/ingenic/ingenic_regs.h      Fri Aug 07 17:31:12 2015 +0000
+++ b/sys/arch/mips/ingenic/ingenic_regs.h      Fri Aug 07 17:37:54 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ingenic_regs.h,v 1.20 2015/07/11 18:54:03 macallan Exp $ */
+/*     $NetBSD: ingenic_regs.h,v 1.21 2015/08/07 17:37:54 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -118,7 +118,7 @@
 static inline void
 writereg(uint32_t reg, uint32_t val)
 {
-       *(int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
+       *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg) = val;
        wbflush();
 }
 
@@ -126,7 +126,7 @@
 readreg(uint32_t reg)
 {
        wbflush();
-       return *(int32_t *)MIPS_PHYS_TO_KSEG1(reg);
+       return *(volatile int32_t *)MIPS_PHYS_TO_KSEG1(reg);
 }
 
 /* extra CP0 registers */
@@ -223,8 +223,8 @@
        #define OPCR_L2CM_ON    0x00000000      /* L2 stays on in sleep */
        #define OPCR_L2CM_RET   0x04000000      /* L2 retention mode in sleep */
        #define OPCR_L2CM_OFF   0x08000000      /* L2 powers down in sleep */
-       #define OPCR_SPENDN0    0x00000080      /* OTG port forced down */
-       #define OPCR_SPENDN1    0x00000040      /* UHC port forced down */
+       #define OPCR_SPENDN0    0x00000080      /* 0 - OTG port forced down */
+       #define OPCR_SPENDN1    0x00000040      /* 0 - UHC port forced down */
        #define OPCR_BUS_MODE   0x00000020      /* 1 - bursts */
        #define OPCR_O1SE       0x00000010      /* EXTCLK on in sleep */
        #define OPCR_PD         0x00000008      /* P0 down in sleep */
@@ -320,6 +320,15 @@
 #define JZ_MSC1CDR     0x100000a4
 #define JZ_MSC2CDR     0x100000a8
 
+/*
+ * random number generator
+ *
+ * Its function currently isn't documented by Ingenic.
+ * However, testing suggests that it works as expected.
+ */
+#define JZ_ERNG        0x100000d8
+#define JZ_RNG 0x100000dc
+
 /* interrupt controller */
 #define JZ_ICSR0       0x10001000      /* raw IRQ line status */
 #define JZ_ICMR0       0x10001004      /* IRQ mask, 1 masks IRQ */