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[src/trunk]: src/sys/external/bsd/dwc2/dist Merge conflicts
details: https://anonhg.NetBSD.org/src/rev/39b3a3c5944e
branches: trunk
changeset: 340297:39b3a3c5944e
user: skrll <skrll%NetBSD.org@localhost>
date: Sun Aug 30 12:59:59 2015 +0000
description:
Merge conflicts
diffstat:
sys/external/bsd/dwc2/dist/dwc2_core.c | 546 +++++++++++++++++++++++++++-
sys/external/bsd/dwc2/dist/dwc2_core.h | 411 +++++++++++++++++++++-
sys/external/bsd/dwc2/dist/dwc2_coreintr.c | 75 +++-
sys/external/bsd/dwc2/dist/dwc2_hcd.c | 163 +++++---
sys/external/bsd/dwc2/dist/dwc2_hcd.h | 33 +-
sys/external/bsd/dwc2/dist/dwc2_hcdintr.c | 107 +++-
sys/external/bsd/dwc2/dist/dwc2_hcdqueue.c | 68 +--
sys/external/bsd/dwc2/dist/dwc2_hw.h | 16 +-
8 files changed, 1190 insertions(+), 229 deletions(-)
diffs (truncated from 2198 to 300 lines):
diff -r c370b948f82f -r 39b3a3c5944e sys/external/bsd/dwc2/dist/dwc2_core.c
--- a/sys/external/bsd/dwc2/dist/dwc2_core.c Sun Aug 30 12:26:29 2015 +0000
+++ b/sys/external/bsd/dwc2/dist/dwc2_core.c Sun Aug 30 12:59:59 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc2_core.c,v 1.7 2015/05/01 06:58:40 hikaru Exp $ */
+/* $NetBSD: dwc2_core.c,v 1.8 2015/08/30 12:59:59 skrll Exp $ */
/*
* core.c - DesignWare HS OTG Controller common routines
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.7 2015/05/01 06:58:40 hikaru Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dwc2_core.c,v 1.8 2015/08/30 12:59:59 skrll Exp $");
#include <sys/types.h>
#include <sys/bus.h>
@@ -67,6 +67,364 @@
#include "dwc2_core.h"
#include "dwc2_hcd.h"
+#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
+/**
+ * dwc2_backup_host_registers() - Backup controller host registers.
+ * When suspending usb bus, registers needs to be backuped
+ * if controller power is disabled once suspended.
+ *
+ * @hsotg: Programming view of the DWC_otg controller
+ */
+static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_hregs_backup *hr;
+ int i;
+
+ dev_dbg(hsotg->dev, "%s\n", __func__);
+
+ /* Backup Host regs */
+ hr = &hsotg->hr_backup;
+ hr->hcfg = DWC2_READ_4(hsotg, HCFG);
+ hr->haintmsk = DWC2_READ_4(hsotg, HAINTMSK);
+ for (i = 0; i < hsotg->core_params->host_channels; ++i)
+ hr->hcintmsk[i] = DWC2_READ_4(hsotg, HCINTMSK(i));
+
+ hr->hprt0 = DWC2_READ_4(hsotg, HPRT0);
+ hr->hfir = DWC2_READ_4(hsotg, HFIR);
+ hr->valid = true;
+
+ return 0;
+}
+
+/**
+ * dwc2_restore_host_registers() - Restore controller host registers.
+ * When resuming usb bus, device registers needs to be restored
+ * if controller power were disabled.
+ *
+ * @hsotg: Programming view of the DWC_otg controller
+ */
+static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_hregs_backup *hr;
+ int i;
+
+ dev_dbg(hsotg->dev, "%s\n", __func__);
+
+ /* Restore host regs */
+ hr = &hsotg->hr_backup;
+ if (!hr->valid) {
+ dev_err(hsotg->dev, "%s: no host registers to restore\n",
+ __func__);
+ return -EINVAL;
+ }
+ hr->valid = false;
+
+ DWC2_WRITE_4(hsotg, HCFG, hr->hcfg);
+ DWC2_WRITE_4(hsotg, HAINTMSK, hr->haintmsk);
+
+ for (i = 0; i < hsotg->core_params->host_channels; ++i)
+ DWC2_WRITE_4(hsotg, HCINTMSK(i), hr->hcintmsk[i]);
+
+ DWC2_WRITE_4(hsotg, HPRT0, hr->hprt0);
+ DWC2_WRITE_4(hsotg, HFIR, hr->hfir);
+
+ return 0;
+}
+#else
+static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
+{ return 0; }
+
+static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
+{ return 0; }
+#endif
+
+#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
+ IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
+/**
+ * dwc2_backup_device_registers() - Backup controller device registers.
+ * When suspending usb bus, registers needs to be backuped
+ * if controller power is disabled once suspended.
+ *
+ * @hsotg: Programming view of the DWC_otg controller
+ */
+static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_dregs_backup *dr;
+ int i;
+
+ dev_dbg(hsotg->dev, "%s\n", __func__);
+
+ /* Backup dev regs */
+ dr = &hsotg->dr_backup;
+
+ dr->dcfg = DWC2_READ_4(hsotg, DCFG);
+ dr->dctl = DWC2_READ_4(hsotg, DCTL);
+ dr->daintmsk = DWC2_READ_4(hsotg, DAINTMSK);
+ dr->diepmsk = DWC2_READ_4(hsotg, DIEPMSK);
+ dr->doepmsk = DWC2_READ_4(hsotg, DOEPMSK);
+
+ for (i = 0; i < hsotg->num_of_eps; i++) {
+ /* Backup IN EPs */
+ dr->diepctl[i] = DWC2_READ_4(hsotg, DIEPCTL(i));
+
+ /* Ensure DATA PID is correctly configured */
+ if (dr->diepctl[i] & DXEPCTL_DPID)
+ dr->diepctl[i] |= DXEPCTL_SETD1PID;
+ else
+ dr->diepctl[i] |= DXEPCTL_SETD0PID;
+
+ dr->dieptsiz[i] = DWC2_READ_4(hsotg, DIEPTSIZ(i));
+ dr->diepdma[i] = DWC2_READ_4(hsotg, DIEPDMA(i));
+
+ /* Backup OUT EPs */
+ dr->doepctl[i] = DWC2_READ_4(hsotg, DOEPCTL(i));
+
+ /* Ensure DATA PID is correctly configured */
+ if (dr->doepctl[i] & DXEPCTL_DPID)
+ dr->doepctl[i] |= DXEPCTL_SETD1PID;
+ else
+ dr->doepctl[i] |= DXEPCTL_SETD0PID;
+
+ dr->doeptsiz[i] = DWC2_READ_4(hsotg, DOEPTSIZ(i));
+ dr->doepdma[i] = DWC2_READ_4(hsotg, DOEPDMA(i));
+ }
+ dr->valid = true;
+ return 0;
+}
+
+/**
+ * dwc2_restore_device_registers() - Restore controller device registers.
+ * When resuming usb bus, device registers needs to be restored
+ * if controller power were disabled.
+ *
+ * @hsotg: Programming view of the DWC_otg controller
+ */
+static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_dregs_backup *dr;
+ u32 dctl;
+ int i;
+
+ dev_dbg(hsotg->dev, "%s\n", __func__);
+
+ /* Restore dev regs */
+ dr = &hsotg->dr_backup;
+ if (!dr->valid) {
+ dev_err(hsotg->dev, "%s: no device registers to restore\n",
+ __func__);
+ return -EINVAL;
+ }
+ dr->valid = false;
+
+ DWC2_WRITE_4(hsotg, DCFG, dr->dcfg);
+ DWC2_WRITE_4(hsotg, DCTL, dr->dctl);
+ DWC2_WRITE_4(hsotg, DAINTMSK, dr->daintmsk);
+ DWC2_WRITE_4(hsotg, DIEPMSK, dr->diepmsk);
+ DWC2_WRITE_4(hsotg, DOEPMSK, dr->doepmsk);
+
+ for (i = 0; i < hsotg->num_of_eps; i++) {
+ /* Restore IN EPs */
+ DWC2_WRITE_4(hsotg, DIEPCTL(i), dr->diepctl[i]);
+ DWC2_WRITE_4(hsotg, DIEPTSIZ(i), dr->dieptsiz[i]);
+ DWC2_WRITE_4(hsotg, DIEPDMA(i), dr->diepdma[i]);
+
+ /* Restore OUT EPs */
+ DWC2_WRITE_4(hsotg, DOEPCTL(i), dr->doepctl[i]);
+ DWC2_WRITE_4(hsotg, DOEPTSIZ(i), dr->doeptsiz[i]);
+ DWC2_WRITE_4(hsotg, DOEPDMA(i), dr->doepdma[i]);
+ }
+
+ /* Set the Power-On Programming done bit */
+ dctl = DWC2_READ_4(hsotg, DCTL);
+ dctl |= DCTL_PWRONPRGDONE;
+ DWC2_WRITE_4(hsotg, DCTL, dctl);
+
+ return 0;
+}
+#else
+static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
+{ return 0; }
+
+static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
+{ return 0; }
+#endif
+
+/**
+ * dwc2_backup_global_registers() - Backup global controller registers.
+ * When suspending usb bus, registers needs to be backuped
+ * if controller power is disabled once suspended.
+ *
+ * @hsotg: Programming view of the DWC_otg controller
+ */
+static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_gregs_backup *gr;
+ int i;
+
+ /* Backup global regs */
+ gr = &hsotg->gr_backup;
+
+ gr->gotgctl = DWC2_READ_4(hsotg, GOTGCTL);
+ gr->gintmsk = DWC2_READ_4(hsotg, GINTMSK);
+ gr->gahbcfg = DWC2_READ_4(hsotg, GAHBCFG);
+ gr->gusbcfg = DWC2_READ_4(hsotg, GUSBCFG);
+ gr->grxfsiz = DWC2_READ_4(hsotg, GRXFSIZ);
+ gr->gnptxfsiz = DWC2_READ_4(hsotg, GNPTXFSIZ);
+ gr->hptxfsiz = DWC2_READ_4(hsotg, HPTXFSIZ);
+ gr->gdfifocfg = DWC2_READ_4(hsotg, GDFIFOCFG);
+ for (i = 0; i < MAX_EPS_CHANNELS; i++)
+ gr->dtxfsiz[i] = DWC2_READ_4(hsotg, DPTXFSIZN(i));
+
+ gr->valid = true;
+ return 0;
+}
+
+/**
+ * dwc2_restore_global_registers() - Restore controller global registers.
+ * When resuming usb bus, device registers needs to be restored
+ * if controller power were disabled.
+ *
+ * @hsotg: Programming view of the DWC_otg controller
+ */
+static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_gregs_backup *gr;
+ int i;
+
+ dev_dbg(hsotg->dev, "%s\n", __func__);
+
+ /* Restore global regs */
+ gr = &hsotg->gr_backup;
+ if (!gr->valid) {
+ dev_err(hsotg->dev, "%s: no global registers to restore\n",
+ __func__);
+ return -EINVAL;
+ }
+ gr->valid = false;
+
+ DWC2_WRITE_4(hsotg, GINTSTS, 0xffffffff);
+ DWC2_WRITE_4(hsotg, GOTGCTL, gr->gotgctl);
+ DWC2_WRITE_4(hsotg, GINTMSK, gr->gintmsk);
+ DWC2_WRITE_4(hsotg, GUSBCFG, gr->gusbcfg);
+ DWC2_WRITE_4(hsotg, GAHBCFG, gr->gahbcfg);
+ DWC2_WRITE_4(hsotg, GRXFSIZ, gr->grxfsiz);
+ DWC2_WRITE_4(hsotg, GNPTXFSIZ, gr->gnptxfsiz);
+ DWC2_WRITE_4(hsotg, HPTXFSIZ, gr->hptxfsiz);
+ DWC2_WRITE_4(hsotg, GDFIFOCFG, gr->gdfifocfg);
+ for (i = 0; i < MAX_EPS_CHANNELS; i++)
+ DWC2_WRITE_4(hsotg, DPTXFSIZN(i), gr->dtxfsiz[i]);
+
+ return 0;
+}
+
+/**
+ * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
+ *
+ * @hsotg: Programming view of the DWC_otg controller
+ * @restore: Controller registers need to be restored
+ */
+int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
+{
+ u32 pcgcctl;
+ int ret = 0;
+
+ if (!hsotg->core_params->hibernation)
+ return -ENOTSUPP;
+
+ pcgcctl = DWC2_READ_4(hsotg, PCGCTL);
+ pcgcctl &= ~PCGCTL_STOPPCLK;
+ DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl);
+
+ pcgcctl = DWC2_READ_4(hsotg, PCGCTL);
+ pcgcctl &= ~PCGCTL_PWRCLMP;
+ DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl);
+
+ pcgcctl = DWC2_READ_4(hsotg, PCGCTL);
+ pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
+ DWC2_WRITE_4(hsotg, PCGCTL, pcgcctl);
+
+ udelay(100);
+ if (restore) {
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