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[src/trunk]: src/sys/arch initialize phy for the third EHCI controller
details: https://anonhg.NetBSD.org/src/rev/20ebf4ee2dfe
branches: trunk
changeset: 341314:20ebf4ee2dfe
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Oct 30 19:11:57 2015 +0000
description:
initialize phy for the third EHCI controller
diffstat:
sys/arch/arm/nvidia/tegra_io.c | 6 ++++--
sys/arch/evbarm/conf/JETSONTK1 | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diffs (45 lines):
diff -r 7512264e9b0d -r 20ebf4ee2dfe sys/arch/arm/nvidia/tegra_io.c
--- a/sys/arch/arm/nvidia/tegra_io.c Fri Oct 30 19:04:21 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_io.c Fri Oct 30 19:11:57 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_io.c,v 1.15 2015/10/21 20:02:12 jmcneill Exp $ */
+/* $NetBSD: tegra_io.c,v 1.16 2015/10/30 19:11:57 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.15 2015/10/21 20:02:12 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.16 2015/10/30 19:11:57 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -126,6 +126,8 @@
TEGRA_USB2_OFFSET, TEGRA_USB2_SIZE, 1, NOINTR },
{ "ehci",
TEGRA_USB2_OFFSET, TEGRA_USB2_SIZE, 1, TEGRA_INTR_USB2 },
+ { "tegrausbphy",
+ TEGRA_USB3_OFFSET, TEGRA_USB3_SIZE, 2, NOINTR },
{ "ehci",
TEGRA_USB3_OFFSET, TEGRA_USB3_SIZE, 2, TEGRA_INTR_USB3 },
};
diff -r 7512264e9b0d -r 20ebf4ee2dfe sys/arch/evbarm/conf/JETSONTK1
--- a/sys/arch/evbarm/conf/JETSONTK1 Fri Oct 30 19:04:21 2015 +0000
+++ b/sys/arch/evbarm/conf/JETSONTK1 Fri Oct 30 19:11:57 2015 +0000
@@ -1,5 +1,5 @@
#
-# $NetBSD: JETSONTK1,v 1.33 2015/10/21 20:02:12 jmcneill Exp $
+# $NetBSD: JETSONTK1,v 1.34 2015/10/30 19:11:57 jmcneill Exp $
#
# NVIDIA Jetson TK1 - Tegra K1 development kit
# https://developer.nvidia.com/jetson-tk1
@@ -155,6 +155,7 @@
# USB 2.0
tegrausbphy0 at tegraio? port 0 # USB PHY1
tegrausbphy1 at tegraio? port 1 # USB PHY2
+tegrausbphy2 at tegraio? port 2 # USB PHY3
ehci0 at tegraio? port 0 # USB1
ehci1 at tegraio? port 1 # USB2
ehci2 at tegraio? port 2 # USB3
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