[src/trunk]: src/sys/arch/mips/mips More of previous, so both kern_intr and u...

[dholland <dholland%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0d7ef0095196
branches:  trunk
changeset: 346280:0d7ef0095196
user:      dholland <dholland%NetBSD.org@localhost>
date:      Mon Jul 04 15:52:31 2016 +0000

description:
More of previous, so both kern_intr and user_intr have the comment.

diffstat:

 sys/arch/mips/mips/locore_mips1.S |   8 ++++++--
 sys/arch/mips/mips/mipsX_subr.S   |  11 ++++++++---
 2 files changed, 14 insertions(+), 5 deletions(-)

diffs (47 lines):

diff -r 24cae20eb3b8 -r 0d7ef0095196 sys/arch/mips/mips/locore_mips1.S
--- a/sys/arch/mips/mips/locore_mips1.S Mon Jul 04 15:47:04 2016 +0000
+++ b/sys/arch/mips/mips/locore_mips1.S Mon Jul 04 15:52:31 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore_mips1.S,v 1.86 2016/07/04 15:47:04 dholland Exp $       */
+/*     $NetBSD: locore_mips1.S,v 1.87 2016/07/04 15:52:31 dholland Exp $       */
 
 /*
  * Copyright (c) 1992, 1993
@@ -495,7 +495,11 @@
        INT_S   t1, CPU_INFO_IDEPTH(s2)         #   store new interrupt depth
 
        /*
-        * Now we can enable interrupts since no interrupts can be delivered
+        * Now that we're at splhigh so all interrupts are masked
+        * individually and we won't get interrupted here, turn the
+        * global interrupt enable bit on again. This will allow
+        * high-priority interrupts to be delivered once a
+        * low-priority interrupt handler lowers spl to execute.
         */
        mfc0    v1, MIPS_COP_0_STATUS
        nop
diff -r 24cae20eb3b8 -r 0d7ef0095196 sys/arch/mips/mips/mipsX_subr.S
--- a/sys/arch/mips/mips/mipsX_subr.S   Mon Jul 04 15:47:04 2016 +0000
+++ b/sys/arch/mips/mips/mipsX_subr.S   Mon Jul 04 15:52:31 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mipsX_subr.S,v 1.66 2016/07/04 15:47:04 dholland Exp $ */
+/*     $NetBSD: mipsX_subr.S,v 1.67 2016/07/04 15:52:31 dholland Exp $ */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -1457,8 +1457,13 @@
        move    s0, v0                          # remember previous priority
 
        /*
-        * Now we can turn off the FPU, clear exception level, and enter
-        * kernel mode since no interrupts can be delivered
+        * Now that we're at splhigh so all interrupts are masked
+        * individually and we won't get interrupted here, clear the
+        * exception level bit. This will allow high-priority
+        * interrupts to be delivered once a low-priority interrupt
+        * handler lowers spl to execute.
+        *
+        * Also turn off the FPU and enter kernel mode.
         */
        mfc0    v1, MIPS_COP_0_STATUS
 #ifdef NOFPU