Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/mips Use sdcache routines.
details: https://anonhg.NetBSD.org/src/rev/928bc8f4a949
branches: trunk
changeset: 346404:928bc8f4a949
user: matt <matt%NetBSD.org@localhost>
date: Mon Jul 11 23:06:53 2016 +0000
description:
Use sdcache routines.
Remove old cache support.
Switch to new cache routines.
diffstat:
sys/arch/mips/conf/files.mips | 14 +-
sys/arch/mips/include/cache_r4k.h | 71 +--
sys/arch/mips/mips/cache.c | 86 ++--
sys/arch/mips/mips/cache_r4k.c | 620 +------------------------------------
4 files changed, 98 insertions(+), 693 deletions(-)
diffs (truncated from 977 to 300 lines):
diff -r 02314fbf264d -r 928bc8f4a949 sys/arch/mips/conf/files.mips
--- a/sys/arch/mips/conf/files.mips Mon Jul 11 19:36:04 2016 +0000
+++ b/sys/arch/mips/conf/files.mips Mon Jul 11 23:06:53 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.mips,v 1.74 2016/07/11 16:15:35 matt Exp $
+# $NetBSD: files.mips,v 1.75 2016/07/11 23:06:53 matt Exp $
#
defflag opt_cputype.h NOFPU FPEMUL
@@ -77,12 +77,12 @@
file arch/mips/mips/cache_mipsNN.c mips32|mips32r2|mips64|mips64r2
file arch/mips/mips/cache_r4k_pcache16.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
file arch/mips/mips/cache_r4k_pcache32.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
-file arch/mips/mips/cache_r4k_pcache64.S mips32|mips32r2|mips64|mips64r2
-file arch/mips/mips/cache_r4k_pcache128.S mips32|mips32r2|mips64|mips64r2
-#file arch/mips/mips/cache_r4k_scache16.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
-#file arch/mips/mips/cache_r4k_scache32.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
-#file arch/mips/mips/cache_r4k_scache64.S mips32|mips32r2|mips64|mips64r2
-#file arch/mips/mips/cache_r4k_scache128.S mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_pcache64.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_pcache128.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_scache16.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_scache32.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_scache64.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
+file arch/mips/mips/cache_r4k_scache128.S mips3|mips4|mips32|mips32r2|mips64|mips64r2
file arch/mips/mips/mips_fputrap.c !nofpu | fpemul
file arch/mips/mips/mips_emul.c
diff -r 02314fbf264d -r 928bc8f4a949 sys/arch/mips/include/cache_r4k.h
--- a/sys/arch/mips/include/cache_r4k.h Mon Jul 11 19:36:04 2016 +0000
+++ b/sys/arch/mips/include/cache_r4k.h Mon Jul 11 23:06:53 2016 +0000
@@ -57,6 +57,7 @@
#if !defined(_LOCORE)
+#if 1
/*
* cache_r4k_op_line:
*
@@ -306,49 +307,15 @@
cache_r4k_op_8lines_NN_4way(64, (va1), (va2), (va3), (va4), (op))
#define cache_r4k_op_8lines_128_4way(va1, va2, va3, va4, op) \
cache_r4k_op_8lines_NN_4way(128, (va1), (va2), (va3), (va4), (op))
-
-void r4k_icache_sync_all_16(void);
-void r4k_icache_sync_range_16(register_t, vsize_t);
-void r4k_icache_sync_range_index_16(vaddr_t, vsize_t);
-
-void r4k_icache_sync_all_32(void);
-void r4k_icache_sync_range_32(register_t, vsize_t);
-void r4k_icache_sync_range_index_32(vaddr_t, vsize_t);
+#endif
-void r4k_pdcache_wbinv_all_16(void);
-void r4k_pdcache_wbinv_range_16(register_t, vsize_t);
-void r4k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t);
-
-void r4k_pdcache_inv_range_16(register_t, vsize_t);
-void r4k_pdcache_wb_range_16(register_t, vsize_t);
-
-void r4k_pdcache_wbinv_all_32(void);
-void r4k_pdcache_wbinv_range_32(register_t, vsize_t);
-void r4k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t);
+/* cache_r4k.c */
-void r4k_pdcache_inv_range_32(register_t, vsize_t);
-void r4k_pdcache_wb_range_32(register_t, vsize_t);
-
-void r4k_sdcache_wbinv_all_32(void);
-void r4k_sdcache_wbinv_range_32(register_t, vsize_t);
-void r4k_sdcache_wbinv_range_index_32(vaddr_t, vsize_t);
-
-void r4k_sdcache_inv_range_32(register_t, vsize_t);
-void r4k_sdcache_wb_range_32(register_t, vsize_t);
-
-void r4k_sdcache_wbinv_all_128(void);
-void r4k_sdcache_wbinv_range_128(register_t, vsize_t);
-void r4k_sdcache_wbinv_range_index_128(vaddr_t, vsize_t);
-
-void r4k_sdcache_inv_range_128(register_t, vsize_t);
-void r4k_sdcache_wb_range_128(register_t, vsize_t);
-
+void r4k_icache_sync_all_generic(void);
+void r4k_icache_sync_range_generic(register_t, vsize_t);
+void r4k_icache_sync_range_index_generic(vaddr_t, vsize_t);
+void r4k_pdcache_wbinv_all_generic(void);
void r4k_sdcache_wbinv_all_generic(void);
-void r4k_sdcache_wbinv_range_generic(register_t, vsize_t);
-void r4k_sdcache_wbinv_range_index_generic(vaddr_t, vsize_t);
-
-void r4k_sdcache_inv_range_generic(register_t, vsize_t);
-void r4k_sdcache_wb_range_generic(register_t, vsize_t);
/* cache_r4k_pcache16.S */
@@ -359,6 +326,13 @@
void cache_r4k_pdcache_hit_wb_inv_16(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_16(register_t, vsize_t);
+/* cache_r4k_scache16.S */
+
+void cache_r4k_sdcache_index_wb_inv_16(vaddr_t, vsize_t);
+void cache_r4k_sdcache_hit_inv_16(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_inv_16(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_16(register_t, vsize_t);
+
/* cache_r4k_pcache32.S */
void cache_r4k_icache_index_inv_32(vaddr_t, vsize_t);
@@ -368,6 +342,13 @@
void cache_r4k_pdcache_hit_wb_inv_32(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_32(register_t, vsize_t);
+/* cache_r4k_scache32.S */
+
+void cache_r4k_sdcache_index_wb_inv_32(vaddr_t, vsize_t);
+void cache_r4k_sdcache_hit_inv_32(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_inv_32(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_32(register_t, vsize_t);
+
/* cache_r4k_pcache64.S */
void cache_r4k_icache_index_inv_64(vaddr_t, vsize_t);
@@ -377,6 +358,13 @@
void cache_r4k_pdcache_hit_wb_inv_64(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_64(register_t, vsize_t);
+/* cache_r4k_scache64.S */
+
+void cache_r4k_sdcache_index_wb_inv_64(vaddr_t, vsize_t);
+void cache_r4k_sdcache_hit_inv_64(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_inv_64(register_t, vsize_t);
+void cache_r4k_sdcache_hit_wb_64(register_t, vsize_t);
+
/* cache_r4k_pcache128.S */
void cache_r4k_icache_index_inv_128(vaddr_t, vsize_t);
@@ -385,6 +373,9 @@
void cache_r4k_pdcache_hit_inv_128(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_inv_128(register_t, vsize_t);
void cache_r4k_pdcache_hit_wb_128(register_t, vsize_t);
+
+/* cache_r4k_scache128.S */
+
void cache_r4k_sdcache_index_wb_inv_128(vaddr_t, vsize_t);
void cache_r4k_sdcache_hit_inv_128(register_t, vsize_t);
void cache_r4k_sdcache_hit_wb_inv_128(register_t, vsize_t);
diff -r 02314fbf264d -r 928bc8f4a949 sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c Mon Jul 11 19:36:04 2016 +0000
+++ b/sys/arch/mips/mips/cache.c Mon Jul 11 23:06:53 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.51 2016/07/11 16:15:36 matt Exp $ */
+/* $NetBSD: cache.c,v 1.52 2016/07/11 23:06:54 matt Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.51 2016/07/11 16:15:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.52 2016/07/11 23:06:54 matt Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@@ -416,23 +416,20 @@
if (mci->mci_pdcache_size > PAGE_SIZE)
mci->mci_cache_virtual_alias = true;
+ mco->mco_icache_sync_all = r4k_icache_sync_all_generic;
switch (mci->mci_picache_line_size) {
case 16:
- mco->mco_icache_sync_all =
- r4k_icache_sync_all_16;
mco->mco_icache_sync_range =
- r4k_icache_sync_range_16;
+ cache_r4k_icache_hit_inv_16;
mco->mco_icache_sync_range_index =
- r4k_icache_sync_range_index_16;
+ cache_r4k_icache_index_inv_16;
break;
case 32:
- mco->mco_icache_sync_all =
- r4k_icache_sync_all_32;
mco->mco_icache_sync_range =
- r4k_icache_sync_range_32;
+ cache_r4k_icache_hit_inv_32;
mco->mco_icache_sync_range_index =
- r4k_icache_sync_range_index_32;
+ cache_r4k_icache_index_inv_32;
break;
default:
@@ -440,31 +437,28 @@
mci->mci_picache_line_size);
}
+ mco->mco_pdcache_wbinv_all = r4k_pdcache_wbinv_all_generic;
switch (mci->mci_pdcache_line_size) {
case 16:
- mco->mco_pdcache_wbinv_all =
- r4k_pdcache_wbinv_all_16;
mco->mco_pdcache_wbinv_range =
- r4k_pdcache_wbinv_range_16;
+ cache_r4k_pdcache_hit_wb_inv_16;
mco->mco_pdcache_wbinv_range_index =
- r4k_pdcache_wbinv_range_index_16;
+ cache_r4k_pdcache_index_wb_inv_16;
mco->mco_pdcache_inv_range =
- r4k_pdcache_inv_range_16;
+ cache_r4k_pdcache_hit_inv_16;
mco->mco_pdcache_wb_range =
- r4k_pdcache_wb_range_16;
+ cache_r4k_pdcache_hit_wb_16;
break;
case 32:
- mco->mco_pdcache_wbinv_all =
- r4k_pdcache_wbinv_all_32;
mco->mco_pdcache_wbinv_range =
- r4k_pdcache_wbinv_range_32;
+ cache_r4k_pdcache_hit_wb_inv_32;
mco->mco_pdcache_wbinv_range_index =
- r4k_pdcache_wbinv_range_index_32;
+ cache_r4k_pdcache_index_wb_inv_32;
mco->mco_pdcache_inv_range =
- r4k_pdcache_inv_range_32;
+ cache_r4k_pdcache_hit_inv_32;
mco->mco_pdcache_wb_range =
- r4k_pdcache_wb_range_32;
+ cache_r4k_pdcache_hit_wb_32;
break;
default:
@@ -730,45 +724,51 @@
#endif
switch (mci->mci_sdcache_ways) {
case 1:
+ mco->mco_sdcache_wbinv_all =
+ r4k_sdcache_wbinv_all_generic;
switch (mci->mci_sdcache_line_size) {
- case 32:
- mco->mco_sdcache_wbinv_all =
- r4k_sdcache_wbinv_all_32;
+ case 16:
mco->mco_sdcache_wbinv_range =
- r4k_sdcache_wbinv_range_32;
+ cache_r4k_sdcache_hit_wb_inv_16;
mco->mco_sdcache_wbinv_range_index =
- r4k_sdcache_wbinv_range_index_32;
+ cache_r4k_sdcache_index_wb_inv_16;
mco->mco_sdcache_inv_range =
- r4k_sdcache_inv_range_32;
+ cache_r4k_sdcache_hit_inv_16;
mco->mco_sdcache_wb_range =
- r4k_sdcache_wb_range_32;
+ cache_r4k_sdcache_hit_wb_16;
break;
- case 16:
- case 64:
- mco->mco_sdcache_wbinv_all =
- r4k_sdcache_wbinv_all_generic;
+ case 32:
mco->mco_sdcache_wbinv_range =
- r4k_sdcache_wbinv_range_generic;
+ cache_r4k_sdcache_hit_wb_inv_32;
mco->mco_sdcache_wbinv_range_index =
- r4k_sdcache_wbinv_range_index_generic;
+ cache_r4k_sdcache_index_wb_inv_32;
mco->mco_sdcache_inv_range =
- r4k_sdcache_inv_range_generic;
+ cache_r4k_sdcache_hit_inv_32;
mco->mco_sdcache_wb_range =
- r4k_sdcache_wb_range_generic;
+ cache_r4k_sdcache_hit_wb_32;
+ break;
+
+ case 64:
+ mco->mco_sdcache_wbinv_range =
+ cache_r4k_sdcache_hit_wb_inv_64;
+ mco->mco_sdcache_wbinv_range_index =
+ cache_r4k_sdcache_index_wb_inv_64;
+ mco->mco_sdcache_inv_range =
+ cache_r4k_sdcache_hit_inv_64;
+ mco->mco_sdcache_wb_range =
+ cache_r4k_sdcache_hit_wb_64;
break;
case 128:
- mco->mco_sdcache_wbinv_all =
- r4k_sdcache_wbinv_all_128;
mco->mco_sdcache_wbinv_range =
- r4k_sdcache_wbinv_range_128;
+ cache_r4k_sdcache_hit_wb_inv_128;
mco->mco_sdcache_wbinv_range_index =
- r4k_sdcache_wbinv_range_index_128;
+ cache_r4k_sdcache_index_wb_inv_128;
mco->mco_sdcache_inv_range =
Home |
Main Index |
Thread Index |
Old Index