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[src/trunk]: src/sys/arch/x86/include KNF so NXR likes it, and some typos
details: https://anonhg.NetBSD.org/src/rev/af72ee8e737f
branches: trunk
changeset: 347262:af72ee8e737f
user: maxv <maxv%NetBSD.org@localhost>
date: Fri Aug 19 18:53:29 2016 +0000
description:
KNF so NXR likes it, and some typos
diffstat:
sys/arch/x86/include/specialreg.h | 754 +++++++++++++++++++-------------------
1 files changed, 377 insertions(+), 377 deletions(-)
diffs (truncated from 993 to 300 lines):
diff -r a87313af714c -r af72ee8e737f sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Fri Aug 19 18:24:57 2016 +0000
+++ b/sys/arch/x86/include/specialreg.h Fri Aug 19 18:53:29 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.88 2016/07/16 13:47:01 maxv Exp $ */
+/* $NetBSD: specialreg.h,v 1.89 2016/08/19 18:53:29 maxv Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -34,12 +34,12 @@
/*
* Bits in 386 special registers:
*/
-#define CR0_PE 0x00000001 /* Protected mode Enable */
-#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
-#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
-#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
-#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
-#define CR0_PG 0x80000000 /* PaGing enable */
+#define CR0_PE 0x00000001 /* Protected mode Enable */
+#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
+#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
+#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
+#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
+#define CR0_PG 0x80000000 /* PaGing enable */
/*
* Bits in 486 special registers:
@@ -47,8 +47,8 @@
#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
#define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
-#define CR0_NW 0x20000000 /* Not Write-through */
-#define CR0_CD 0x40000000 /* Cache Disable */
+#define CR0_NW 0x20000000 /* Not Write-through */
+#define CR0_CD 0x40000000 /* Cache Disable */
/*
* Cyrix 486 DLC special registers, accessible as IO ports.
@@ -94,14 +94,14 @@
/*
* Extended Control Register XCR0
*/
-#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
-#define XCR0_SSE 0x00000002 /* SSE state */
-#define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */
-#define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */
-#define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */
-#define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */
-#define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */
-#define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */
+#define XCR0_X87 0x00000001 /* x87 FPU/MMX state */
+#define XCR0_SSE 0x00000002 /* SSE state */
+#define XCR0_YMM_Hi128 0x00000004 /* AVX-256 (ymmn registers) */
+#define XCR0_BNDREGS 0x00000008 /* Memory protection ext bounds */
+#define XCR0_BNDCSR 0x00000010 /* Memory protection ext state */
+#define XCR0_Opmask 0x00000020 /* AVX-512 Opmask */
+#define XCR0_ZMM_Hi256 0x00000040 /* AVX-512 upper 256 bits low regs */
+#define XCR0_Hi16_ZMM 0x00000080 /* AVX-512 512 bits upper registers */
/*
* Known fpu bits - only these get enabled
@@ -125,38 +125,38 @@
*/
/* Fn00000001 %edx features */
-#define CPUID_FPU 0x00000001 /* processor has an FPU? */
-#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
-#define CPUID_DE 0x00000004 /* has debugging extension */
-#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
-#define CPUID_TSC 0x00000010 /* has time stamp counter */
-#define CPUID_MSR 0x00000020 /* has mode specific registers */
-#define CPUID_PAE 0x00000040 /* has phys address extension */
-#define CPUID_MCE 0x00000080 /* has machine check exception */
-#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
-#define CPUID_APIC 0x00000200 /* has enabled APIC */
-#define CPUID_B10 0x00000400 /* reserved, MTRR */
-#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
-#define CPUID_MTRR 0x00001000 /* has memory type range register */
-#define CPUID_PGE 0x00002000 /* has page global extension */
-#define CPUID_MCA 0x00004000 /* has machine check architecture */
-#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
-#define CPUID_PAT 0x00010000 /* Page Attribute Table */
-#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
-#define CPUID_PN 0x00040000 /* processor serial number */
-#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
-#define CPUID_B20 0x00100000 /* reserved */
-#define CPUID_DS 0x00200000 /* Debug Store */
-#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
-#define CPUID_MMX 0x00800000 /* MMX supported */
-#define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
-#define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
-#define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
-#define CPUID_SS 0x08000000 /* self-snoop */
-#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
-#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
-#define CPUID_IA64 0x40000000 /* IA-64 architecture */
-#define CPUID_SBF 0x80000000 /* signal break on FERR */
+#define CPUID_FPU 0x00000001 /* processor has an FPU? */
+#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
+#define CPUID_DE 0x00000004 /* has debugging extension */
+#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
+#define CPUID_TSC 0x00000010 /* has time stamp counter */
+#define CPUID_MSR 0x00000020 /* has mode specific registers */
+#define CPUID_PAE 0x00000040 /* has phys address extension */
+#define CPUID_MCE 0x00000080 /* has machine check exception */
+#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
+#define CPUID_APIC 0x00000200 /* has enabled APIC */
+#define CPUID_B10 0x00000400 /* reserved, MTRR */
+#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
+#define CPUID_MTRR 0x00001000 /* has memory type range register */
+#define CPUID_PGE 0x00002000 /* has page global extension */
+#define CPUID_MCA 0x00004000 /* has machine check architecture */
+#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
+#define CPUID_PAT 0x00010000 /* Page Attribute Table */
+#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
+#define CPUID_PN 0x00040000 /* processor serial number */
+#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
+#define CPUID_B20 0x00100000 /* reserved */
+#define CPUID_DS 0x00200000 /* Debug Store */
+#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
+#define CPUID_MMX 0x00800000 /* MMX supported */
+#define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
+#define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
+#define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
+#define CPUID_SS 0x08000000 /* self-snoop */
+#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
+#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
+#define CPUID_IA64 0x40000000 /* IA-64 architecture */
+#define CPUID_SBF 0x80000000 /* signal break on FERR */
#define CPUID_FLAGS1 "\20" \
"\1" "FPU" "\2" "VME" "\3" "DE" "\4" "PSE" \
@@ -180,38 +180,38 @@
* CPUID "features" bits in Fn00000001 %ecx
*/
-#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
-#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
-#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
-#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
-#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
-#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
-#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
-#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
-#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
+#define CPUID2_SSE3 0x00000001 /* Streaming SIMD Extensions 3 */
+#define CPUID2_PCLMUL 0x00000002 /* PCLMULQDQ instructions */
+#define CPUID2_DTES64 0x00000004 /* 64-bit Debug Trace */
+#define CPUID2_MONITOR 0x00000008 /* MONITOR/MWAIT instructions */
+#define CPUID2_DS_CPL 0x00000010 /* CPL Qualified Debug Store */
+#define CPUID2_VMX 0x00000020 /* Virtual Machine Extensions */
+#define CPUID2_SMX 0x00000040 /* Safer Mode Extensions */
+#define CPUID2_EST 0x00000080 /* Enhanced SpeedStep Technology */
+#define CPUID2_TM2 0x00000100 /* Thermal Monitor 2 */
#define CPUID2_SSSE3 0x00000200 /* Supplemental SSE3 */
-#define CPUID2_CID 0x00000400 /* Context ID */
-#define CPUID2_SDBG 0x00000800 /* Silicon Debug */
-#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
-#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
-#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
-#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
+#define CPUID2_CID 0x00000400 /* Context ID */
+#define CPUID2_SDBG 0x00000800 /* Silicon Debug */
+#define CPUID2_FMA 0x00001000 /* has Fused Multiply Add */
+#define CPUID2_CX16 0x00002000 /* has CMPXCHG16B instruction */
+#define CPUID2_xTPR 0x00004000 /* Task Priority Messages disabled? */
+#define CPUID2_PDCM 0x00008000 /* Perf/Debug Capability MSR */
/* bit 16 unused 0x00010000 */
-#define CPUID2_PCID 0x00020000 /* Process Context ID */
-#define CPUID2_DCA 0x00040000 /* Direct Cache Access */
-#define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
-#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
-#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
-#define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */
-#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
-#define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */
-#define CPUID2_AES 0x02000000 /* AES instructions */
-#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
-#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
-#define CPUID2_AVX 0x10000000 /* AVX instructions */
-#define CPUID2_F16C 0x20000000 /* half precision conversion */
-#define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */
-#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
+#define CPUID2_PCID 0x00020000 /* Process Context ID */
+#define CPUID2_DCA 0x00040000 /* Direct Cache Access */
+#define CPUID2_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
+#define CPUID2_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
+#define CPUID2_X2APIC 0x00200000 /* xAPIC Extensions */
+#define CPUID2_MOVBE 0x00400000 /* MOVBE (move after byteswap) */
+#define CPUID2_POPCNT 0x00800000 /* popcount instruction available */
+#define CPUID2_DEADLINE 0x01000000 /* APIC Timer supports TSC Deadline */
+#define CPUID2_AES 0x02000000 /* AES instructions */
+#define CPUID2_XSAVE 0x04000000 /* XSAVE instructions */
+#define CPUID2_OSXSAVE 0x08000000 /* XGETBV/XSETBV instructions */
+#define CPUID2_AVX 0x10000000 /* AVX instructions */
+#define CPUID2_F16C 0x20000000 /* half precision conversion */
+#define CPUID2_RDRAND 0x40000000 /* RDRAND (hardware random number) */
+#define CPUID2_RAZ 0x80000000 /* RAZ. Indicates guest state. */
#define CPUID2_FLAGS1 "\20" \
"\1" "SSE3" "\2" "PCLMULQDQ" "\3" "DTES64" "\4" "MONITOR" \
@@ -312,7 +312,7 @@
/*
* Intel Structured Extended Feature leaf Fn0000_0007
* %eax == 0: Subleaf 0
- * %eax: The Maximun input value for supported subleaf.
+ * %eax: The Maximum input value for supported subleaf.
* %ebx: Feature bits.
* %ecx: Feature bits.
*/
@@ -378,11 +378,11 @@
* %ecx == 0: supported features info:
* %eax: Valid bits of lower 32bits of XCR0
* %ebx: Maximum save area size for features enabled in XCR0
- * %ecx: Maximim save area size for all cpu features
+ * %ecx: Maximum save area size for all cpu features
* %edx: Valid bits of upper 32bits of XCR0
*
* %ecx == 1:
- * %eax: Bit 0 => xsaveopt instruction avalaible (sandy bridge onwards)
+ * %eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards)
* %ebx: Save area size for features enabled by XCR0 | IA32_XSS
* %ecx: Valid bits of lower 32bits of IA32_XSS
* %edx: Valid bits of upper 32bits of IA32_XSS
@@ -395,10 +395,10 @@
*/
/* %ecx=1 %eax */
-#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
-#define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */
-#define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */
-#define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */
+#define CPUID_PES1_XSAVEOPT 0x00000001 /* xsaveopt instruction */
+#define CPUID_PES1_XSAVEC 0x00000002 /* xsavec & compacted XRSTOR */
+#define CPUID_PES1_XGETBV 0x00000004 /* xgetbv with ECX = 1 */
+#define CPUID_PES1_XSAVES 0x00000008 /* xsaves/xrstors, IA32_XSS */
#define CPUID_PES1_FLAGS "\20" \
"\1" "XSAVEOPT" "\2" "XSAVEC" "\3" "XGETBV" "\4" "XSAVES"
@@ -406,8 +406,8 @@
/* Intel Fn80000001 extended features - %edx */
#define CPUID_SYSCALL 0x00000800 /* SYSCALL/SYSRET */
#define CPUID_XD 0x00100000 /* Execute Disable (like CPUID_NOX) */
-#define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */
-#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
+#define CPUID_P1GB 0x04000000 /* 1GB Large Page Support */
+#define CPUID_RDTSCP 0x08000000 /* Read TSC Pair Instruction */
#define CPUID_EM64T 0x20000000 /* Intel EM64T */
#define CPUID_INTEL_EXT_FLAGS "\20" \
@@ -415,11 +415,11 @@
"\34" "RDTSCP" "\36" "EM64T"
/* Intel Fn80000001 extended features - %ecx */
-#define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
+#define CPUID_LAHF 0x00000001 /* LAHF/SAHF in IA-32e mode, 64bit sub*/
/* 0x00000020 */ /* LZCNT. Same as AMD's CPUID_LZCNT */
-#define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */
+#define CPUID_PREFETCHW 0x00000100 /* PREFETCHW */
-#define CPUID_INTEL_FLAGS4 "\20" \
+#define CPUID_INTEL_FLAGS4 "\20" \
"\1" "LAHF" "\02" "B01" "\03" "B02" \
"\06" "LZCNT" \
"\11" "PREFETCHW"
@@ -504,16 +504,16 @@
"\15" "B12"
/* AMD Fn8000000a %edx features (SVM features) */
-#define CPUID_AMD_SVM_NP 0x00000001
-#define CPUID_AMD_SVM_LbrVirt 0x00000002
-#define CPUID_AMD_SVM_SVML 0x00000004
-#define CPUID_AMD_SVM_NRIPS 0x00000008
-#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
-#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
-#define CPUID_AMD_SVM_FlushByASID 0x00000040
-#define CPUID_AMD_SVM_DecodeAssist 0x00000080
-#define CPUID_AMD_SVM_PauseFilter 0x00000400
-#define CPUID_AMD_SVM_FLAGS "\20" \
+#define CPUID_AMD_SVM_NP 0x00000001
+#define CPUID_AMD_SVM_LbrVirt 0x00000002
+#define CPUID_AMD_SVM_SVML 0x00000004
+#define CPUID_AMD_SVM_NRIPS 0x00000008
+#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
+#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
+#define CPUID_AMD_SVM_FlushByASID 0x00000040
+#define CPUID_AMD_SVM_DecodeAssist 0x00000080
+#define CPUID_AMD_SVM_PauseFilter 0x00000400
+#define CPUID_AMD_SVM_FLAGS "\20" \
"\1" "NP" "\2" "LbrVirt" "\3" "SVML" "\4" "NRIPS" \
"\5" "TSCRate" "\6" "VMCBCleanBits" \
"\7" "FlushByASID" "\10" "DecodeAssist" \
@@ -545,18 +545,18 @@
#define MSR_P5_MC_ADDR 0x000 /* P5 only */
#define MSR_P5_MC_TYPE 0x001 /* P5 only */
#define MSR_TSC 0x010
-#define MSR_CESR 0x011 /* P5 only (trap on P6) */
-#define MSR_CTR0 0x012 /* P5 only (trap on P6) */
-#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
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