[src/trunk]: src/sys/arch/mips/ingenic fix comments, add LCDC*_BASEs

[macallan <macallan%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/cd5b9571396b
branches:  trunk
changeset: 337629:cd5b9571396b
user:      macallan <macallan%NetBSD.org@localhost>
date:      Tue Apr 21 19:19:31 2015 +0000

description:
fix comments, add LCDC*_BASEs

diffstat:

 sys/arch/mips/ingenic/ingenic_regs.h |  13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)

diffs (44 lines):

diff -r f9fd6276d505 -r cd5b9571396b sys/arch/mips/ingenic/ingenic_regs.h
--- a/sys/arch/mips/ingenic/ingenic_regs.h      Tue Apr 21 17:39:50 2015 +0000
+++ b/sys/arch/mips/ingenic/ingenic_regs.h      Tue Apr 21 19:19:31 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ingenic_regs.h,v 1.12 2015/03/25 11:23:26 macallan Exp $ */
+/*     $NetBSD: ingenic_regs.h,v 1.13 2015/04/21 19:19:31 macallan Exp $ */
 
 /*-
  * Copyright (c) 2014 Michael Lorenz
@@ -26,11 +26,12 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <mips/locore.h>
-
 #ifndef INGENIC_REGS_H
 #define INGENIC_REGS_H
 
+/* for wbflush() */
+#include <mips/locore.h>
+
 /* UARTs, mostly 16550 compatible with 32bit spaced registers */
 #define JZ_UART0 0x10030000
 #define JZ_UART1 0x10031000
@@ -38,6 +39,10 @@
 #define JZ_UART3 0x10033000
 #define JZ_UART4 0x10034000
 
+/* LCD controller base addresses, registers are in jzfb_regs.h */
+#define JZ_LCDC0_BASE 0x13050000
+#define JZ_LCDC1_BASE 0x130a0000
+
 /* watchdog */
 #define JZ_WDOG_TDR    0x10002000      /* compare */
 #define JZ_WDOG_TCER   0x10002004
@@ -459,7 +464,7 @@
        #define JZ_TXABT        0x40    /* ABORT occured */
        #define JZ_TXEMP        0x10    /* TX FIFO is low */
        #define JZ_TXOF         0x08    /* TX FIFO is high */
-       #define JZ_RXFL         0x04    /* RX FIFO is low */
+       #define JZ_RXFL         0x04    /* RX FIFO is at  JZ_SMBRXTL*/
        #define JZ_RXOF         0x02    /* RX FIFO is high */
        #define JZ_RXUF         0x01    /* RX FIFO underflow */
 #define JZ_SMBINTM     0x30 /* SMB Interrupt Mask */