[src/trunk]: src/sys/arch/arm/nvidia add pllc and uart rate funcs

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/08b88d09dcd1
branches:  trunk
changeset: 337922:08b88d09dcd1
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun May 03 16:40:12 2015 +0000

description:
add pllc and uart rate funcs

diffstat:

 sys/arch/arm/nvidia/tegra_car.c    |  46 ++++++++++++++++++++++++++++++++++++-
 sys/arch/arm/nvidia/tegra_carreg.h |  34 +++++++++++++++++++++++++++-
 sys/arch/arm/nvidia/tegra_var.h    |   4 ++-
 3 files changed, 80 insertions(+), 4 deletions(-)

diffs (151 lines):

diff -r 82f8a36a2f9e -r 08b88d09dcd1 sys/arch/arm/nvidia/tegra_car.c
--- a/sys/arch/arm/nvidia/tegra_car.c   Sun May 03 16:18:51 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_car.c   Sun May 03 16:40:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_car.c,v 1.3 2015/05/03 11:47:15 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.4 2015/05/03 16:40:12 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.3 2015/05/03 11:47:15 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.4 2015/05/03 16:40:12 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -132,6 +132,13 @@
 }
 
 u_int
+tegra_car_pllc_rate(void)
+{
+       return tegra_car_pll_rate(CAR_PLLC_BASE_REG, CAR_PLLC_BASE_DIVM,
+           CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP);
+}
+
+u_int
 tegra_car_pllp0_rate(void)
 {
        return tegra_car_pll_rate(CAR_PLLP_BASE_REG, CAR_PLLP_BASE_DIVM,
@@ -139,6 +146,41 @@
 }
 
 u_int
+tegra_car_uart_rate(u_int port)
+{
+       bus_space_tag_t bst;
+       bus_space_handle_t bsh;
+       bus_size_t src_reg;
+       u_int src_rate;
+
+       tegra_car_get_bs(&bst, &bsh);
+
+       switch (port) {
+       case 0: src_reg = CAR_CLKSRC_UARTA_REG; break;
+       case 1: src_reg = CAR_CLKSRC_UARTB_REG; break;
+       case 2: src_reg = CAR_CLKSRC_UARTC_REG; break;
+       case 3: src_reg = CAR_CLKSRC_UARTD_REG; break;
+       default: return 0;
+       }
+
+       const uint32_t src = bus_space_read_4(bst, bsh, src_reg);
+       switch (__SHIFTOUT(src, CAR_CLKSRC_UART_SRC)) {
+       case 0:
+               src_rate = tegra_car_pllp0_rate();
+               break;
+       default:
+               panic("%s: unsupported src %#x", __func__, src);
+       }
+
+       if (__SHIFTOUT(src, CAR_CLKSRC_UART_DIV_ENB)) {
+               const u_int div = __SHIFTOUT(src, CAR_CLKSRC_UART_DIV) + 1;
+               return src_rate / div;
+       } else {
+               return src_rate;
+       }
+}
+
+u_int
 tegra_car_periph_sdmmc_rate(u_int port)
 {
        bus_space_tag_t bst;
diff -r 82f8a36a2f9e -r 08b88d09dcd1 sys/arch/arm/nvidia/tegra_carreg.h
--- a/sys/arch/arm/nvidia/tegra_carreg.h        Sun May 03 16:18:51 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_carreg.h        Sun May 03 16:40:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_carreg.h,v 1.3 2015/05/03 11:47:15 jmcneill Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.4 2015/05/03 16:40:12 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -45,8 +45,25 @@
 
 #define CAR_PLLP_OUTA_REG      0xa4
 #define CAR_PLLP_OUTB_REG      0xa8
+#define CAR_PLLP_OUTB_OUT4_RATIO       __BITS(31,24)
+#define CAR_PLLP_OUTB_OUT4_OVRRIDE     __BIT(18)
+#define CAR_PLLP_OUTB_OUT4_CLKEN       __BIT(17)
+#define CAR_PLLP_OUTB_OUT4_RSTN                __BIT(16)
+#define CAR_PLLP_OUTB_OUT3_RATIO       __BITS(15,8)
+#define CAR_PLLP_OUTB_OUT3_OVRRIDE     __BIT(2)
+#define CAR_PLLP_OUTB_OUT3_CLKEN       __BIT(1)
+#define CAR_PLLP_OUTB_OUT3_RSTN                __BIT(0)
 #define CAR_PLLP_MISC_REG      0xac
 
+#define CAR_PLLC_BASE_REG      0x80
+#define CAR_PLLC_BASE_ENABLE           __BIT(30)
+#define CAR_PLLC_BASE_REF_DIS          __BIT(29)
+#define CAR_PLLC_BASE_LOCK_OVERRIDE    __BIT(28)
+#define CAR_PLLC_BASE_LOCK             __BIT(27)
+#define CAR_PLLC_BASE_DIVP             __BITS(23,20)
+#define CAR_PLLC_BASE_DIVN             __BITS(15,8)
+#define CAR_PLLC_BASE_DIVM             __BITS(7,0)
+
 #define CAR_PLLX_BASE_REG      0xe0
 #define CAR_PLLX_BASE_BYPASS           __BIT(31)
 #define CAR_PLLX_BASE_ENABLE           __BIT(30)
@@ -58,6 +75,21 @@
 
 #define CAR_PLLX_MISC_REG      0xe8
 
+#define CAR_CLKSRC_UARTA_REG           0x178
+#define CAR_CLKSRC_UARTB_REG           0x17c
+#define CAR_CLKSRC_UARTC_REG           0x1a0
+#define CAR_CLKSRC_UARTD_REG           0x1c0
+
+#define CAR_CLKSRC_UART_SRC            __BITS(31,29)
+#define CAR_CLKSRC_UART_SRC_PLLP_OUT0  0
+#define CAR_CLKSRC_UART_SRC_PLLC2_OUT0 1
+#define CAR_CLKSRC_UART_SRC_PLLC_OUT0  2
+#define CAR_CLKSRC_UART_SRC_PLLC3_OUT0 3
+#define CAR_CLKSRC_UART_SRC_PLLM_OUT0  4
+#define CAR_CLKSRC_UART_SRC_CLK_M      6
+#define CAR_CLKSRC_UART_DIV_ENB                __BIT(24)
+#define CAR_CLKSRC_UART_DIV            __BITS(15,0)
+
 #define CAR_CLKSRC_SDMMC1_REG          0x150
 #define CAR_CLKSRC_SDMMC2_REG          0x154
 #define CAR_CLKSRC_SDMMC4_REG          0x164
diff -r 82f8a36a2f9e -r 08b88d09dcd1 sys/arch/arm/nvidia/tegra_var.h
--- a/sys/arch/arm/nvidia/tegra_var.h   Sun May 03 16:18:51 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_var.h   Sun May 03 16:40:12 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_var.h,v 1.7 2015/05/03 01:07:44 jmcneill Exp $ */
+/* $NetBSD: tegra_var.h,v 1.8 2015/05/03 16:40:12 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -74,8 +74,10 @@
 void   tegra_dma_bootstrap(psize_t);
 
 u_int  tegra_car_osc_rate(void);
+u_int  tegra_car_pllc_rate(void);
 u_int  tegra_car_pllx_rate(void);
 u_int  tegra_car_pllp0_rate(void);
+u_int  tegra_car_uart_rate(u_int);
 u_int  tegra_car_periph_sdmmc_rate(u_int);
 int    tegra_car_periph_sdmmc_set_div(u_int, u_int);