Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/arm/nvidia add Tegra MPIO / Pinmux driver
details: https://anonhg.NetBSD.org/src/rev/8706d9f758e2
branches: trunk
changeset: 338000:8706d9f758e2
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Thu May 07 23:55:11 2015 +0000
description:
add Tegra MPIO / Pinmux driver
diffstat:
sys/arch/arm/nvidia/files.tegra | 7 +-
sys/arch/arm/nvidia/tegra_io.c | 6 +-
sys/arch/arm/nvidia/tegra_mpio.c | 598 ++++++++++++++++++++++++++++++++++++
sys/arch/arm/nvidia/tegra_mpioreg.h | 277 ++++++++++++++++
sys/arch/arm/nvidia/tegra_reg.h | 4 +-
sys/arch/arm/nvidia/tegra_var.h | 23 +-
6 files changed, 910 insertions(+), 5 deletions(-)
diffs (truncated from 986 to 300 lines):
diff -r a1fc75f339eb -r 8706d9f758e2 sys/arch/arm/nvidia/files.tegra
--- a/sys/arch/arm/nvidia/files.tegra Thu May 07 19:14:55 2015 +0000
+++ b/sys/arch/arm/nvidia/files.tegra Thu May 07 23:55:11 2015 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.7 2015/05/05 00:25:44 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.8 2015/05/07 23:55:11 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -41,6 +41,11 @@
attach tegragpio at tegraio with tegra_gpio
file arch/arm/nvidia/tegra_gpio.c tegra_gpio
+# MPIO / Pinmux
+device tegrampio
+attach tegrampio at tegraio with tegra_mpio
+file arch/arm/nvidia/tegra_mpio.c tegra_mpio
+
# UART
attach com at tegraio with tegra_com
file arch/arm/nvidia/tegra_com.c tegra_com needs-flag
diff -r a1fc75f339eb -r 8706d9f758e2 sys/arch/arm/nvidia/tegra_io.c
--- a/sys/arch/arm/nvidia/tegra_io.c Thu May 07 19:14:55 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_io.c Thu May 07 23:55:11 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_io.c,v 1.6 2015/05/05 00:25:44 jmcneill Exp $ */
+/* $NetBSD: tegra_io.c,v 1.7 2015/05/07 23:55:11 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.6 2015/05/05 00:25:44 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.7 2015/05/07 23:55:11 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -73,6 +73,8 @@
TEGRA_MC_OFFSET, TEGRA_MC_SIZE, NOPORT, NOINTR },
{ "tegrapmc",
TEGRA_PMC_OFFSET, TEGRA_PMC_SIZE, NOPORT, NOINTR },
+ { "tegrampio",
+ TEGRA_MPIO_OFFSET, TEGRA_MPIO_SIZE, NOPORT, NOINTR },
{ "com",
TEGRA_UARTA_OFFSET, TEGRA_UARTA_SIZE, 0, TEGRA_INTR_UARTA },
{ "com",
diff -r a1fc75f339eb -r 8706d9f758e2 sys/arch/arm/nvidia/tegra_mpio.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/nvidia/tegra_mpio.c Thu May 07 23:55:11 2015 +0000
@@ -0,0 +1,598 @@
+/* $NetBSD: tegra_mpio.c,v 1.1 2015/05/07 23:55:11 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+#include "opt_ddb.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_mpio.c,v 1.1 2015/05/07 23:55:11 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/kmem.h>
+#include <sys/gpio.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_mpioreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+static int tegra_mpio_match(device_t, cfdata_t, void *);
+static void tegra_mpio_attach(device_t, device_t, void *);
+
+struct tegra_mpio_padgrp {
+ u_int pg_reg;
+ uint32_t pg_preemp;
+ uint32_t pg_hsm;
+ uint32_t pg_schmt;
+ uint32_t pg_drv_type;
+ uint32_t pg_drvdn;
+ uint32_t pg_drvup;
+ uint32_t pg_slwr;
+ uint32_t pg_slwf;
+};
+
+#define PADGRP(_n, _p, _dt, _dd, _du, _slwf) \
+ { \
+ .pg_reg = PADGRP_ ## _n ## _REG,\
+ .pg_preemp = (_p), \
+ .pg_hsm = __BIT(2), \
+ .pg_schmt = __BIT(3), \
+ .pg_drv_type = (_dt), \
+ .pg_drvdn = (_dd), \
+ .pg_drvup = (_du), \
+ .pg_slwr = __BITS(29,28), \
+ .pg_slwf = (_slwf) \
+ }
+
+static const struct tegra_mpio_padgrp tegra_mpio_padgrp[] = {
+ PADGRP(GMACFG, __BIT(0), __BITS(7,6), __BITS(18,14), __BITS(24,20), __BITS(31,30)),
+ PADGRP(SDIO1CFG, 0, 0, __BITS(18,12), __BITS(26,20), __BITS(31,30)),
+ PADGRP(SDIO3CFG, 0, 0, __BITS(18,12), __BITS(26,20), __BITS(31,30)),
+ PADGRP(SDIO4CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(AOCFG0, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(AOCFG1, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(AOCFG2, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(AOCFG3, 0, 0, __BITS(16,12), 0, 0),
+ PADGRP(AOCFG4, 0, __BITS(7,6), __BITS(18,12), __BITS(26,20), __BITS(31,30)),
+ PADGRP(CDEV1CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(CDEV2CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(CECCFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(DAP1CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(DAP2CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(DAP3CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(DAP4CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(DAP5CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(DBGCFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(DDCCFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(DEV3CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(OWRCFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(SPICFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(UAACFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(UABCFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(UART2CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(UART3CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(UDACFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(ATCFG1, 0, __BITS(7,6), __BITS(18,12), __BITS(26,20), __BITS(31,30)),
+ PADGRP(ATCFG2, 0, __BITS(7,6), __BITS(18,12), __BITS(26,20), __BITS(31,30)),
+ PADGRP(ATCFG3, 0, __BITS(7,6), __BITS(18,12), __BITS(26,20), __BITS(31,30)),
+ PADGRP(ATCFG4, 0, __BITS(7,6), __BITS(18,12), __BITS(26,20), __BITS(31,30)),
+ PADGRP(ATCFG5, 0, 0, __BITS(18,14), __BITS(23,19), __BITS(31,30)),
+ PADGRP(ATCFG6, 0, __BITS(7,6), __BITS(18,12), __BITS(26,20), __BITS(31,30)),
+ PADGRP(GMECFG, 0, 0, __BITS(18,14), __BITS(23,19), __BITS(31,30)),
+ PADGRP(GMFCFG, 0, 0, __BITS(18,14), __BITS(23,19), __BITS(31,30)),
+ PADGRP(GMGCFG, 0, 0, __BITS(18,14), __BITS(23,19), __BITS(31,30)),
+ PADGRP(GMHCFG, 0, 0, __BITS(18,14), __BITS(23,19), __BITS(31,30)),
+ PADGRP(HVCFG0, 0, 0, __BITS(16,12), 0, 0),
+ PADGRP(GPVCFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+ PADGRP(USB_VBUS_EN_CFG, 0, 0, __BITS(16,12), __BITS(24,20), __BITS(31,30)),
+};
+
+struct tegra_mpio_pinmux {
+ u_int pm_reg;
+ const char * pm_func[4];
+ int pm_flags;
+#define MPIOF_OD 0x1
+#define MPIOF_IO_RESET 0x2
+#define MPIOF_RCV_SEL 0x4
+};
+
+static const struct tegra_mpio_pinmux tegra_mpio_pinmux[] = {
+ { PINMUX_AUX_ULPI_DATA0_REG, { "spi3", "hsi", "uarta", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_DATA1_REG, { "spi3", "hsi", "uarta", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_DATA2_REG, { "spi3", "hsi", "uarta", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_DATA3_REG, { "spi3", "hsi", "uarta", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_DATA4_REG, { "spi3", "hsi", "uarta", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_DATA5_REG, { "spi3", "hsi", "uarta", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_DATA6_REG, { "spi3", "hsi", "uarta", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_DATA7_REG, { "spi3", "hsi", "uarta", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_CLK_REG, { "spi1", "spi5", "uartd", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_DIR_REG, { "spi1", "spi5", "uartd", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_NXT_REG, { "spi1", "spi5", "uartd", "ulpi" }, 0 },
+ { PINMUX_AUX_ULPI_STP_REG, { "spi1", "spi5", "uartd", "ulpi" }, 0 },
+ { PINMUX_AUX_DAP3_FS_REG, { "i2s2", "spi5", "displaya", "displayb" }, 0 },
+ { PINMUX_AUX_DAP3_DIN_REG, { "i2s2", "spi5", "displaya", "displayb" }, 0 },
+ { PINMUX_AUX_DAP3_DOUT_REG, { "i2s2", "spi5", "displaya", NULL }, 0 },
+ { PINMUX_AUX_DAP3_SCLK_REG, { "i2s2", "spi5", NULL, "displayb" }, 0 },
+ { PINMUX_AUX_GPIO_PV0_REG, { NULL, NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_GPIO_PV1_REG, { NULL, NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_SDMMC1_CLK_REG, { "sdmmc1", "clk12", NULL, NULL }, 0 },
+ { PINMUX_AUX_SDMMC1_CMD_REG, { "sdmmc1", "spdif", "spi4", "uarta" }, 0 },
+ { PINMUX_AUX_SDMMC1_DAT3_REG, { "sdmmc1", "spdif", "spi4", "uarta" }, 0 },
+ { PINMUX_AUX_SDMMC1_DAT2_REG, { "sdmmc1", "pwm0", "spi4", "uarta" }, 0 },
+ { PINMUX_AUX_SDMMC1_DAT1_REG, { "sdmmc1", "pwm1", "spi4", "uarta" }, 0 },
+ { PINMUX_AUX_SDMMC1_DAT0_REG, { "sdmmc1", NULL, "spi4", "uarta" }, 0 },
+ { PINMUX_AUX_CLK2_OUT_REG, { "extperiph2", NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_CLK2_REQ_REG, { "dap", NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_HDMI_INT_REG, { NULL, NULL, NULL, NULL }, MPIOF_RCV_SEL },
+ { PINMUX_AUX_DDC_SCL_REG, { "i2c4", NULL, NULL, NULL }, MPIOF_RCV_SEL },
+ { PINMUX_AUX_DDC_SDA_REG, { "i2c4", NULL, NULL, NULL }, MPIOF_RCV_SEL },
+ { PINMUX_AUX_UART2_RXD_REG, { "irda", "spdif", "uarta", "spi4" }, 0 },
+ { PINMUX_AUX_UART2_TXD_REG, { "irda", "spdif", "uarta", "spi4" }, 0 },
+ { PINMUX_AUX_UART2_RTS_N_REG, { "uarta", "uartb", "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_UART2_CTS_N_REG, { "uarta", "uartb", "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_UART3_TXD_REG, { "uartc", NULL, "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_UART3_RXD_REG, { "uartc", NULL, "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_UART3_CTS_N_REG, { "uartc", "sdmmc1", "dtv", "gmi" }, 0 },
+ { PINMUX_AUX_UART3_RTS_N_REG, { "uartc", "pwm0", "dtv", "gmi" }, 0 },
+ { PINMUX_AUX_GPIO_PU0_REG, { "owr", "uarta", "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PU1_REG, { NULL, "uarta", "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PU2_REG, { NULL, "uarta", "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PU3_REG, { "pwm0", "uarta", "gmi", "displayb" }, 0 },
+ { PINMUX_AUX_GPIO_PU4_REG, { "pwm1", "uarta", "gmi", "displayb" }, 0 },
+ { PINMUX_AUX_GPIO_PU5_REG, { "pwm2", "uarta", "gmi", "displayb" }, 0 },
+ { PINMUX_AUX_GPIO_PU6_REG, { "pwm3", "uarta", NULL, "gmi" }, 0 },
+ { PINMUX_AUX_GEN1_I2C_SDA_REG, { "i2c1", NULL, NULL, NULL }, MPIOF_OD },
+ { PINMUX_AUX_GEN1_I2C_SCL_REG, { "i2c1", NULL, NULL, NULL }, MPIOF_OD },
+ { PINMUX_AUX_DAP4_FS_REG, { "i2s3", "gmi", "dtv", NULL }, 0 },
+ { PINMUX_AUX_DAP4_DIN_REG, { "i2s3", "gmi", NULL, NULL }, 0 },
+ { PINMUX_AUX_DAP4_DOUT_REG, { "i2s3", "gmi", "dtv", NULL }, 0 },
+ { PINMUX_AUX_DAP4_SCLK_REG, { "i2s3", "gmi", NULL, NULL }, 0 },
+ { PINMUX_AUX_CLK3_OUT_REG, { "extperiph3", NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_CLK3_REQ_REG, { "dev3", NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_GPIO_PC7_REG, { NULL, NULL, "gmi", "gmi_alt" }, 0 },
+ { PINMUX_AUX_GPIO_PI5_REG, { "sdmmc2a", NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PI7_REG, { NULL, "trace", "gmi", "dtv" }, 0 },
+ { PINMUX_AUX_GPIO_PK0_REG, { NULL, "sdmmc3", "gmi", "soc" }, 0 },
+ { PINMUX_AUX_GPIO_PK1_REG, { "sdmmc2a", "trace", "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PJ0_REG, { NULL, NULL, "gmi", "usb" }, 0 },
+ { PINMUX_AUX_GPIO_PJ2_REG, { NULL, NULL, "gmi", "soc" }, 0 },
+ { PINMUX_AUX_GPIO_PK3_REG, { "sdmmc2a", "trace", "gmi", "ccla" }, 0 },
+ { PINMUX_AUX_GPIO_PK4_REG, { "sdmmc2a", NULL, "gmi", "gmi_alt" }, 0 },
+ { PINMUX_AUX_GPIO_PK2_REG, { NULL, NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PI3_REG, { NULL, NULL, "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_GPIO_PI6_REG, { NULL, NULL, "gmi", "sdmmc2a" }, 0 },
+ { PINMUX_AUX_GPIO_PG0_REG, { NULL, NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PG1_REG, { NULL, NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PG2_REG, { NULL, "trace", "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PG3_REG, { NULL, "trace", "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PG4_REG, { NULL, "tmds", "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_GPIO_PG5_REG, { NULL, NULL, "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_GPIO_PG6_REG, { NULL, NULL, "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_GPIO_PG7_REG, { NULL, NULL, "gmi", "spi4" }, 0 },
+ { PINMUX_AUX_GPIO_PH0_REG, { "pwm0", "trace", "gmi", "dtv" }, 0 },
+ { PINMUX_AUX_GPIO_PH1_REG, { "pwm1", "tmds", "gmi", "displaya" }, 0 },
+ { PINMUX_AUX_GPIO_PH2_REG, { "pwm2", "tmds", "gmi", "cldvfs" }, 0 },
+ { PINMUX_AUX_GPIO_PH3_REG, { "pwm3", "spi4", "gmi", "cldvfs" }, 0 },
+ { PINMUX_AUX_GPIO_PH4_REG, { "sdmmc2a", NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PH5_REG, { "sdmmc2a", NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PH6_REG, { "sdmmc2a", "trace", "gmi", "dtv" }, 0 },
+ { PINMUX_AUX_GPIO_PH7_REG, { "sdmmc2a", "trace", "gmi", "dtv" }, 0 },
+ { PINMUX_AUX_GPIO_PJ7_REG, { "uartd", NULL, "gmi", "gmi_alt" }, 0 },
+ { PINMUX_AUX_GPIO_PB0_REG, { "uartd", NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PB1_REG, { "uartd", NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PK7_REG, { "uartd", NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PI0_REG, { NULL, NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PI1_REG, { NULL, NULL, "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PI2_REG, { "sdmmc2a", "trace", "gmi", NULL }, 0 },
+ { PINMUX_AUX_GPIO_PI4_REG, { "spi4", "trace", "gmi", "displaya" }, 0 },
+ { PINMUX_AUX_GEN2_I2C_SCL_REG, { "i2c2", NULL, "gmi", NULL }, MPIOF_OD },
+ { PINMUX_AUX_GEN2_I2C_SDA_REG, { "i2c2", NULL, "gmi", NULL }, MPIOF_OD },
+ { PINMUX_AUX_SDMMC4_CLK_REG, { "sdmmc4", NULL, "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_CMD_REG, { "sdmmc4", NULL, "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_DAT0_REG, { "sdmmc4", "spi3", "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_DAT1_REG, { "sdmmc4", "spi3", "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_DAT2_REG, { "sdmmc4", "spi3", "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_DAT3_REG, { "sdmmc4", "spi3", "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_DAT4_REG, { "sdmmc4", "spi3", "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_DAT5_REG, { "sdmmc4", "spi3", NULL, NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_DAT6_REG, { "sdmmc4", "spi3", "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_SDMMC4_DAT7_REG, { "sdmmc4", NULL, "gmi", NULL }, MPIOF_IO_RESET },
+ { PINMUX_AUX_CAM_MCLK_REG, { "vi", "vi_alt1", "vi_alt3", "sdmmc2b" }, 0 },
+ { PINMUX_AUX_GPIO_PCC1_REG, { "i2s4", NULL, NULL, "sdmmc2b" }, 0 },
+ { PINMUX_AUX_GPIO_PBB0_REG, { "vgp6", "vimclk2", "sdmmc2b", "vimclk2_alt" }, 0 },
+ { PINMUX_AUX_CAM_I2C_SCL_REG, { "vgp1", "i2c3", NULL, "sdmmc2b" }, MPIOF_OD },
+ { PINMUX_AUX_CAM_I2C_SDA_REG, { "vgp2", "i2c3", NULL, "sdmmc2b" }, MPIOF_OD },
+ { PINMUX_AUX_GPIO_PBB3_REG, { "vgp3", "displaya", "displayb", "sdmmc2b" }, 0 },
+ { PINMUX_AUX_GPIO_PBB4_REG, { "vgp4", "displaya", "displayb", "sdmmc2b" }, 0 },
+ { PINMUX_AUX_GPIO_PBB5_REG, { "vgp5", "displaya", NULL, "sdmmc2b" }, 0 },
+ { PINMUX_AUX_GPIO_PBB6_REG, { "i2s4", NULL, "displayb", "sdmmc2b" }, 0 },
+ { PINMUX_AUX_GPIO_PBB7_REG, { "i2s4", NULL, NULL, "sdmmc2b" }, 0 },
+ { PINMUX_AUX_GPIO_PCC2_REG, { "i2s4", NULL, "sdmmc3", "sdmmc2b" }, 0 },
+ { PINMUX_AUX_JTAG_RTCK_REG, { "rtck", NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_PWR_I2C_SCL_REG, { "i2cpwr", NULL, NULL, NULL }, MPIOF_OD },
+ { PINMUX_AUX_PWR_I2C_SDA_REG, { "i2cpwr", NULL, NULL, NULL }, MPIOF_OD },
+ { PINMUX_AUX_KB_ROW0_REG, { "kbc", NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_KB_ROW1_REG, { "kbc", NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_KB_ROW2_REG, { "kbc", NULL, NULL, NULL }, 0 },
+ { PINMUX_AUX_KB_ROW3_REG, { "kbc", "displaya", "sys", "displayb" }, 0 },
+ { PINMUX_AUX_KB_ROW4_REG, { "kbc", "displaya", NULL, "displayb" }, 0 },
Home |
Main Index |
Thread Index |
Old Index