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[src/trunk]: src/sys/dev/pci - printf->DPRINTF in wm_serdes_mediastatus().
details: https://anonhg.NetBSD.org/src/rev/d55baba0c991
branches: trunk
changeset: 342738:d55baba0c991
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Thu Jan 07 10:08:18 2016 +0000
description:
- printf->DPRINTF in wm_serdes_mediastatus().
- KNF.
diffstat:
sys/dev/pci/if_wm.c | 312 ++++++++++++++++++++++++++--------------------------
1 files changed, 156 insertions(+), 156 deletions(-)
diffs (truncated from 896 to 300 lines):
diff -r 99e38ec0a7b4 -r d55baba0c991 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Thu Jan 07 08:58:01 2016 +0000
+++ b/sys/dev/pci/if_wm.c Thu Jan 07 10:08:18 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.387 2015/12/25 05:45:40 msaitoh Exp $ */
+/* $NetBSD: if_wm.c,v 1.388 2016/01/07 10:08:18 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -83,7 +83,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.387 2015/12/25 05:45:40 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.388 2016/01/07 10:08:18 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -310,7 +310,7 @@
bus_addr_t rxq_rdt_reg; /* offset of RDT register */
- int rxq_ptr; /* next ready Rx descriptor/queue ent */
+ int rxq_ptr; /* next ready Rx desc/queue ent */
int rxq_discard;
int rxq_len;
struct mbuf *rxq_head;
@@ -406,7 +406,7 @@
struct evcnt sc_ev_txtsopain; /* painful header manip. for TSO */
struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
- struct evcnt sc_ev_txdrop; /* Tx packets dropped (too many segs) */
+ struct evcnt sc_ev_txdrop; /* Tx packets dropped(too many segs) */
struct evcnt sc_ev_tu; /* Tx underrun */
@@ -1408,7 +1408,7 @@
rxd->wrx_status = 0;
rxd->wrx_errors = 0;
rxd->wrx_special = 0;
- wm_cdrxsync(rxq, start, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+ wm_cdrxsync(rxq, start, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
CSR_WRITE(sc, rxq->rxq_rdt_reg, start);
}
@@ -1494,7 +1494,7 @@
sc->sc_dmat = pa->pa_dmat;
sc->sc_pcidevid = PCI_PRODUCT(pa->pa_id);
- sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG));
+ sc->sc_rev = PCI_REVISION(pci_conf_read(pc, pa->pa_tag,PCI_CLASS_REG));
pci_aprint_devinfo_fancy(pa, "Ethernet controller", wmp->wmp_name, 1);
sc->sc_type = wmp->wmp_type;
@@ -1741,11 +1741,9 @@
pcix_sts = pci_conf_read(pa->pa_pc, pa->pa_tag,
sc->sc_pcixe_capoff + PCIX_STATUS);
- bytecnt =
- (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >>
+ bytecnt = (pcix_cmd & PCIX_CMD_BYTECNT_MASK) >>
PCIX_CMD_BYTECNT_SHIFT;
- maxb =
- (pcix_sts & PCIX_STATUS_MAXB_MASK) >>
+ maxb = (pcix_sts & PCIX_STATUS_MAXB_MASK) >>
PCIX_STATUS_MAXB_SHIFT;
if (bytecnt > maxb) {
aprint_verbose_dev(sc->sc_dev,
@@ -1895,7 +1893,7 @@
/* FLASH */
sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_LOCK_EXTCNF;
sc->sc_nvm_wordsize = 2048;
- memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH);
+ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,WM_ICH8_FLASH);
if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
&sc->sc_flasht, &sc->sc_flashh, NULL, &sc->sc_flashs)) {
aprint_error_dev(sc->sc_dev,
@@ -1904,11 +1902,10 @@
}
reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *
- ICH_FLASH_SECTOR_SIZE;
+ ICH_FLASH_SECTOR_SIZE;
sc->sc_ich8_flash_bank_size =
((reg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
- sc->sc_ich8_flash_bank_size -=
- (reg & ICH_GFPREG_BASE_MASK);
+ sc->sc_ich8_flash_bank_size -= (reg & ICH_GFPREG_BASE_MASK);
sc->sc_ich8_flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
sc->sc_ich8_flash_bank_size /= 2 * sizeof(uint16_t);
break;
@@ -2755,7 +2752,7 @@
if (change != 0)
sc->sc_if_flags = ifp->if_flags;
- if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) {
+ if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
rc = ENETRESET;
goto out;
}
@@ -3982,7 +3979,7 @@
m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
- BUS_DMA_READ|BUS_DMA_NOWAIT);
+ BUS_DMA_READ | BUS_DMA_NOWAIT);
if (error) {
/* XXX XXX XXX */
aprint_error_dev(sc->sc_dev,
@@ -4383,8 +4380,7 @@
intrstr = pci_intr_string(pc, sc->sc_intrs[intr_idx], intrbuf,
sizeof(intrbuf));
#ifdef WM_MPSAFE
- pci_intr_setattr(pc, &sc->sc_intrs[intr_idx],
- PCI_INTR_MPSAFE, true);
+ pci_intr_setattr(pc, &sc->sc_intrs[intr_idx], PCI_INTR_MPSAFE, true);
#endif
memset(intr_xname, 0, sizeof(intr_xname));
snprintf(intr_xname, sizeof(intr_xname), "%sLINK",
@@ -4412,13 +4408,13 @@
fail_1:
for (qidx = 0; qidx < rx_established; qidx++) {
struct wm_rxqueue *rxq = &sc->sc_rxq[qidx];
- pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[rxq->rxq_intr_idx]);
+ pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[rxq->rxq_intr_idx]);
sc->sc_ihs[rxq->rxq_intr_idx] = NULL;
}
fail_0:
for (qidx = 0; qidx < tx_established; qidx++) {
struct wm_txqueue *txq = &sc->sc_txq[qidx];
- pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[txq->txq_intr_idx]);
+ pci_intr_disestablish(sc->sc_pc,sc->sc_ihs[txq->txq_intr_idx]);
sc->sc_ihs[txq->txq_intr_idx] = NULL;
}
@@ -4601,8 +4597,7 @@
*/
wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
0xFFFF);
- val = wm_kmrn_readreg(sc,
- KUMCTRLSTA_OFFSET_INB_PARAM);
+ val = wm_kmrn_readreg(sc, KUMCTRLSTA_OFFSET_INB_PARAM);
val |= 0x3F;
wm_kmrn_writereg(sc,
KUMCTRLSTA_OFFSET_INB_PARAM, val);
@@ -4643,6 +4638,9 @@
/* Set up MSI-X */
if (sc->sc_nintrs > 1) {
uint32_t ivar;
+ struct wm_txqueue *txq;
+ struct wm_rxqueue *rxq;
+ int qid;
if (sc->sc_type == WM_T_82575) {
/* Interrupt control */
@@ -4652,13 +4650,13 @@
/* TX */
for (i = 0; i < sc->sc_ntxqueues; i++) {
- struct wm_txqueue *txq = &sc->sc_txq[i];
+ txq = &sc->sc_txq[i];
CSR_WRITE(sc, WMREG_MSIXBM(txq->txq_intr_idx),
EITR_TX_QUEUE(txq->txq_id));
}
/* RX */
for (i = 0; i < sc->sc_nrxqueues; i++) {
- struct wm_rxqueue *rxq = &sc->sc_rxq[i];
+ rxq = &sc->sc_rxq[i];
CSR_WRITE(sc, WMREG_MSIXBM(rxq->rxq_intr_idx),
EITR_RX_QUEUE(rxq->rxq_id));
}
@@ -4674,25 +4672,26 @@
ivar = 0;
/* TX */
for (i = 0; i < sc->sc_ntxqueues; i++) {
- struct wm_txqueue *txq = &sc->sc_txq[i];
- ivar |= __SHIFTIN((IVAR_VALID_82574|txq->txq_intr_idx),
+ txq = &sc->sc_txq[i];
+ ivar |= __SHIFTIN((IVAR_VALID_82574
+ | txq->txq_intr_idx),
IVAR_TX_MASK_Q_82574(txq->txq_id));
}
/* RX */
for (i = 0; i < sc->sc_nrxqueues; i++) {
- struct wm_rxqueue *rxq = &sc->sc_rxq[i];
- ivar |= __SHIFTIN((IVAR_VALID_82574|rxq->rxq_intr_idx),
+ rxq = &sc->sc_rxq[i];
+ ivar |= __SHIFTIN((IVAR_VALID_82574
+ | rxq->rxq_intr_idx),
IVAR_RX_MASK_Q_82574(rxq->rxq_id));
}
/* Link status */
- ivar |= __SHIFTIN((IVAR_VALID_82574|sc->sc_link_intr_idx),
- IVAR_OTHER_MASK);
+ ivar |= __SHIFTIN((IVAR_VALID_82574
+ | sc->sc_link_intr_idx), IVAR_OTHER_MASK);
CSR_WRITE(sc, WMREG_IVAR, ivar | IVAR_INT_ON_ALL_WB);
} else {
/* Interrupt control */
- CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR
- | GPIE_MULTI_MSIX | GPIE_EIAME
- | GPIE_PBA);
+ CSR_WRITE(sc, WMREG_GPIE, GPIE_NSICR | GPIE_MULTI_MSIX
+ | GPIE_EIAME | GPIE_PBA);
switch (sc->sc_type) {
case WM_T_82580:
@@ -4702,51 +4701,55 @@
case WM_T_I211:
/* TX */
for (i = 0; i < sc->sc_ntxqueues; i++) {
- struct wm_txqueue *txq = &sc->sc_txq[i];
- int qid = txq->txq_id;
+ txq = &sc->sc_txq[i];
+ qid = txq->txq_id;
ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
ivar &= ~IVAR_TX_MASK_Q(qid);
- ivar |= __SHIFTIN(
- (txq->txq_intr_idx | IVAR_VALID),
- IVAR_TX_MASK_Q(qid));
+ ivar |= __SHIFTIN((txq->txq_intr_idx
+ | IVAR_VALID),
+ IVAR_TX_MASK_Q(qid));
CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
}
/* RX */
for (i = 0; i < sc->sc_nrxqueues; i++) {
- struct wm_rxqueue *rxq = &sc->sc_rxq[i];
- int qid = rxq->rxq_id;
+ rxq = &sc->sc_rxq[i];
+ qid = rxq->rxq_id;
ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
ivar &= ~IVAR_RX_MASK_Q(qid);
- ivar |= __SHIFTIN(
- (rxq->rxq_intr_idx | IVAR_VALID),
- IVAR_RX_MASK_Q(qid));
+ ivar |= __SHIFTIN((rxq->rxq_intr_idx
+ | IVAR_VALID),
+ IVAR_RX_MASK_Q(qid));
CSR_WRITE(sc, WMREG_IVAR_Q(qid), ivar);
}
break;
case WM_T_82576:
/* TX */
for (i = 0; i < sc->sc_ntxqueues; i++) {
- struct wm_txqueue *txq = &sc->sc_txq[i];
- int qid = txq->txq_id;
- ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(qid));
+ txq = &sc->sc_txq[i];
+ qid = txq->txq_id;
+ ivar = CSR_READ(sc,
+ WMREG_IVAR_Q_82576(qid));
ivar &= ~IVAR_TX_MASK_Q_82576(qid);
- ivar |= __SHIFTIN(
- (txq->txq_intr_idx | IVAR_VALID),
- IVAR_TX_MASK_Q_82576(qid));
- CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid), ivar);
+ ivar |= __SHIFTIN((txq->txq_intr_idx
+ | IVAR_VALID),
+ IVAR_TX_MASK_Q_82576(qid));
+ CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid),
+ ivar);
}
/* RX */
for (i = 0; i < sc->sc_nrxqueues; i++) {
- struct wm_rxqueue *rxq = &sc->sc_rxq[i];
- int qid = rxq->rxq_id;
- ivar = CSR_READ(sc, WMREG_IVAR_Q_82576(qid));
+ rxq = &sc->sc_rxq[i];
+ qid = rxq->rxq_id;
+ ivar = CSR_READ(sc,
+ WMREG_IVAR_Q_82576(qid));
ivar &= ~IVAR_RX_MASK_Q_82576(qid);
- ivar |= __SHIFTIN(
- (rxq->rxq_intr_idx | IVAR_VALID),
- IVAR_RX_MASK_Q_82576(qid));
- CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid), ivar);
+ ivar |= __SHIFTIN((rxq->rxq_intr_idx
+ | IVAR_VALID),
+ IVAR_RX_MASK_Q_82576(qid));
+ CSR_WRITE(sc, WMREG_IVAR_Q_82576(qid),
+ ivar);
}
break;
default:
@@ -4780,6 +4783,9 @@
ICR_RXO | ICR_RXT0;
if (sc->sc_nintrs > 1) {
uint32_t mask;
+ struct wm_txqueue *txq;
+ struct wm_rxqueue *rxq;
+
switch (sc->sc_type) {
case WM_T_82574:
CSR_WRITE(sc, WMREG_EIAC_82574,
@@ -4791,22 +4797,22 @@
if (sc->sc_type == WM_T_82575) {
mask = 0;
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