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[src/trunk]: src/sys/arch Trailing whitespace
details: https://anonhg.NetBSD.org/src/rev/1952aa1c0e49
branches: trunk
changeset: 347459:1952aa1c0e49
user: skrll <skrll%NetBSD.org@localhost>
date: Sat Aug 27 05:52:43 2016 +0000
description:
Trailing whitespace
diffstat:
sys/arch/evbmips/ingenic/intr.c | 20 +++++++++---------
sys/arch/evbmips/loongson/loongson_intr.c | 8 +++---
sys/arch/mips/ingenic/ingenic_regs.h | 34 +++++++++++++++---------------
3 files changed, 31 insertions(+), 31 deletions(-)
diffs (213 lines):
diff -r 5adf033f0e84 -r 1952aa1c0e49 sys/arch/evbmips/ingenic/intr.c
--- a/sys/arch/evbmips/ingenic/intr.c Sat Aug 27 03:58:13 2016 +0000
+++ b/sys/arch/evbmips/ingenic/intr.c Sat Aug 27 05:52:43 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.c,v 1.11 2016/08/26 15:45:48 skrll Exp $ */
+/* $NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.11 2016/08/26 15:45:48 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.12 2016/08/27 05:52:43 skrll Exp $");
#define __INTR_PRIVATE
@@ -143,7 +143,7 @@
uint32_t id;
#ifdef INGENIC_INTR_DEBUG
char buffer[256];
-
+
#if 0
snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending,
MFC0(MIPS_COP_0_CAUSE, 0));
@@ -172,7 +172,7 @@
#ifdef MULTIPROCESSOR
uint32_t tag;
tag = MFC0(CP0_CORE_MBOX, 0);
-
+
ipi_process(curcpu(), tag);
#ifdef INGENIC_INTR_DEBUG
snprintf(buffer, 256,
@@ -222,9 +222,9 @@
* but I haven't seen them there so for now we just weed them
* out right here.
* The idea is to allow peripheral interrupts on both cores but
- * block INT0 on core1 so it would see only timer interrupts
+ * block INT0 on core1 so it would see only timer interrupts
* and IPIs. If that doesn't work we'll have to send an IPI to
- * core1 for each timer tick.
+ * core1 for each timer tick.
*/
mask = readreg(JZ_ICPR0);
if (mask & 0x0c000000) {
@@ -268,13 +268,13 @@
if (intrs[idx].ih_func != NULL) {
if (intrs[idx].ih_ipl == IPL_VM)
KERNEL_LOCK(1, NULL);
- intrs[idx].ih_func(intrs[idx].ih_arg);
+ intrs[idx].ih_func(intrs[idx].ih_arg);
if (intrs[idx].ih_ipl == IPL_VM)
KERNEL_UNLOCK_ONE(NULL);
} else {
/* spurious interrupt, mask it */
writereg(JZ_ICMSR0, mask);
- }
+ }
irql &= ~mask;
bit = ffs32(irql);
bail--;
@@ -296,13 +296,13 @@
if (intrs[idx].ih_func != NULL) {
if (intrs[idx].ih_ipl == IPL_VM)
KERNEL_LOCK(1, NULL);
- intrs[idx].ih_func(intrs[idx].ih_arg);
+ intrs[idx].ih_func(intrs[idx].ih_arg);
if (intrs[idx].ih_ipl == IPL_VM)
KERNEL_UNLOCK_ONE(NULL);
} else {
/* spurious interrupt, mask it */
writereg(JZ_ICMSR1, mask);
- }
+ }
irqh &= ~mask;
bit = ffs32(irqh);
}
diff -r 5adf033f0e84 -r 1952aa1c0e49 sys/arch/evbmips/loongson/loongson_intr.c
--- a/sys/arch/evbmips/loongson/loongson_intr.c Sat Aug 27 03:58:13 2016 +0000
+++ b/sys/arch/evbmips/loongson/loongson_intr.c Sat Aug 27 05:52:43 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: loongson_intr.c,v 1.5 2016/08/26 15:45:48 skrll Exp $ */
+/* $NetBSD: loongson_intr.c,v 1.6 2016/08/27 05:53:40 skrll Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: loongson_intr.c,v 1.5 2016/08/26 15:45:48 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: loongson_intr.c,v 1.6 2016/08/27 05:53:40 skrll Exp $");
#define __INTR_PRIVATE
@@ -179,7 +179,7 @@
loongson_pciide_compat_intr_establish(void *v, device_t dev,
const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg)
{
- pci_chipset_tag_t pc = pa->pa_pc;
+ pci_chipset_tag_t pc = pa->pa_pc;
void *cookie;
int bus, irq;
char buf[PCI_INTRSTR_LEN];
@@ -235,7 +235,7 @@
const char *
loongson_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
{
-
+
const struct bonito_config *bc = v;
return loongson_intr_string(bc, ih, buf, len);
}
diff -r 5adf033f0e84 -r 1952aa1c0e49 sys/arch/mips/ingenic/ingenic_regs.h
--- a/sys/arch/mips/ingenic/ingenic_regs.h Sat Aug 27 03:58:13 2016 +0000
+++ b/sys/arch/mips/ingenic/ingenic_regs.h Sat Aug 27 05:52:43 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ingenic_regs.h,v 1.23 2016/04/07 01:00:05 macallan Exp $ */
+/* $NetBSD: ingenic_regs.h,v 1.24 2016/08/27 05:56:33 skrll Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -63,15 +63,15 @@
/* timers and PWMs */
#define JZ_TC_TER 0x10002010 /* TC enable reg, ro */
#define JZ_TC_TESR 0x10002014 /* TC enable set reg. */
- #define TESR_TCST0 0x0001 /* enable counter 0 */
- #define TESR_TCST1 0x0002 /* enable counter 1 */
- #define TESR_TCST2 0x0004 /* enable counter 2 */
- #define TESR_TCST3 0x0008 /* enable counter 3 */
- #define TESR_TCST4 0x0010 /* enable counter 4 */
- #define TESR_TCST5 0x0020 /* enable counter 5 */
- #define TESR_TCST6 0x0040 /* enable counter 6 */
- #define TESR_TCST7 0x0080 /* enable counter 7 */
- #define TESR_OST 0x8000 /* enable OST */
+ #define TESR_TCST0 0x0001 /* enable counter 0 */
+ #define TESR_TCST1 0x0002 /* enable counter 1 */
+ #define TESR_TCST2 0x0004 /* enable counter 2 */
+ #define TESR_TCST3 0x0008 /* enable counter 3 */
+ #define TESR_TCST4 0x0010 /* enable counter 4 */
+ #define TESR_TCST5 0x0020 /* enable counter 5 */
+ #define TESR_TCST6 0x0040 /* enable counter 6 */
+ #define TESR_TCST7 0x0080 /* enable counter 7 */
+ #define TESR_OST 0x8000 /* enable OST */
#define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */
#define JZ_TC_TFR 0x10002020
#define TFR_FFLAG0 0x00000001 /* channel 0 */
@@ -167,7 +167,7 @@
#define CP0_CORE_MBOX 20 /* select 0 for core 0, 1 for 1 */
#define CP0_CORE0_MBOX _(20), 0
-#define CP0_CORE1_MBOX _(20), 1
+#define CP0_CORE1_MBOX _(20), 1
@@ -289,7 +289,7 @@
#define PCR_CLK_48 0x02000000 /* 48MHz */
#define PCR_CLK_24 0x01000000 /* 24MHz */
#define PCR_CLK_12 0x00000000 /* 12MHz */
- #define PCR_DMPD1 0x00800000 /* pull down D- on port 1 */
+ #define PCR_DMPD1 0x00800000 /* pull down D- on port 1 */
#define PCR_DPPD1 0x00400000 /* pull down D+ on port 1 */
#define PCR_PORT0_RST 0x00200000 /* port 0 reset */
#define PCR_PORT1_RST 0x00100000 /* port 1 reset */
@@ -399,7 +399,7 @@
/*
* INT == 1: 0 - level triggered, 1 - edge triggered
* INT == 0: 0 - device select, see below
- */
+ */
#define JZ_GPIO_PAT1 0x00000030 /* pattern 1 register */
#define JZ_GPIO_PAT1S 0x00000034 /* pattern 1 set register */
#define JZ_GPIO_PAT1C 0x00000038 /* pattern 1 clear register */
@@ -468,7 +468,7 @@
writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */
writereg(reg + JZ_GPIO_PAT0C, mask);
}
-
+
static inline void
gpio_as_dev1(uint32_t g, int pin)
{
@@ -480,7 +480,7 @@
writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */
writereg(reg + JZ_GPIO_PAT0S, mask);
}
-
+
static inline void
gpio_as_dev2(uint32_t g, int pin)
{
@@ -492,7 +492,7 @@
writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */
writereg(reg + JZ_GPIO_PAT0C, mask);
}
-
+
static inline void
gpio_as_dev3(uint32_t g, int pin)
{
@@ -504,7 +504,7 @@
writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */
writereg(reg + JZ_GPIO_PAT0S, mask);
}
-
+
static inline void
gpio_as_intr_level(uint32_t g, int pin)
{
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