[src/trunk]: src/sys/arch/arm/nvidia when setting sdmmc divisor, do a full re...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/d6e27db800f7
branches:  trunk
changeset: 337915:d6e27db800f7
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun May 03 11:47:15 2015 +0000

description:
when setting sdmmc divisor, do a full reset / enable sequence

diffstat:

 sys/arch/arm/nvidia/tegra_car.c    |  45 +++++++++++++++++++++++++++++++------
 sys/arch/arm/nvidia/tegra_carreg.h |  15 +++++++++++-
 2 files changed, 51 insertions(+), 9 deletions(-)

diffs (107 lines):

diff -r 21dfb2b2ed00 -r d6e27db800f7 sys/arch/arm/nvidia/tegra_car.c
--- a/sys/arch/arm/nvidia/tegra_car.c   Sun May 03 11:46:44 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_car.c   Sun May 03 11:47:15 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_car.c,v 1.2 2015/05/02 14:10:03 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.3 2015/05/03 11:47:15 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.2 2015/05/02 14:10:03 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.3 2015/05/03 11:47:15 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -167,7 +167,8 @@
 {
        bus_space_tag_t bst;
        bus_space_handle_t bsh;
-       bus_size_t src_reg;
+       bus_size_t src_reg, rst_reg, enb_reg;
+       u_int dev_bit;
        uint32_t src;
 
        KASSERT(div > 0);
@@ -175,18 +176,46 @@
        tegra_car_get_bs(&bst, &bsh);
 
        switch (port) {
-       case 0: src_reg = CAR_CLKSRC_SDMMC1_REG; break;
-       case 1: src_reg = CAR_CLKSRC_SDMMC2_REG; break;
-       case 2: src_reg = CAR_CLKSRC_SDMMC3_REG; break;
-       case 3: src_reg = CAR_CLKSRC_SDMMC4_REG; break;
+       case 0:
+               src_reg = CAR_CLKSRC_SDMMC1_REG;
+               rst_reg = CAR_RST_DEV_L_SET_REG;
+               enb_reg = CAR_CLK_ENB_L_SET_REG;
+               dev_bit = CAR_DEV_L_SDMMC1;
+               break;
+       case 1:
+               src_reg = CAR_CLKSRC_SDMMC2_REG;
+               rst_reg = CAR_RST_DEV_L_SET_REG;
+               enb_reg = CAR_CLK_ENB_L_SET_REG;
+               dev_bit = CAR_DEV_L_SDMMC2;
+               break;
+       case 2:
+               src_reg = CAR_CLKSRC_SDMMC3_REG;
+               rst_reg = CAR_RST_DEV_U_SET_REG;
+               enb_reg = CAR_CLK_ENB_U_SET_REG;
+               dev_bit = CAR_DEV_U_SDMMC3;
+               break;
+       case 3:
+               src_reg = CAR_CLKSRC_SDMMC4_REG;
+               rst_reg = CAR_RST_DEV_L_SET_REG;
+               enb_reg = CAR_CLK_ENB_L_SET_REG;
+               dev_bit = CAR_DEV_L_SDMMC4;
+               break;
        default: return EINVAL;
        }
 
+       /* enter reset */
+       bus_space_write_4(bst, bsh, rst_reg, dev_bit);
+       /* enable clk */
+       bus_space_write_4(bst, bsh, enb_reg, dev_bit);
+
+       /* update clk div */
        src = __SHIFTIN(CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0,
                        CAR_CLKSRC_SDMMC_SRC);
        src |= __SHIFTIN(div - 1, CAR_CLKSRC_SDMMC_DIV);
+       bus_space_write_4(bst, bsh, src_reg, src);
 
-       bus_space_write_4(bst, bsh, src_reg, src);
+       /* leave reset */
+       bus_space_write_4(bst, bsh, rst_reg+4, dev_bit);
 
        return 0;
 }
diff -r 21dfb2b2ed00 -r d6e27db800f7 sys/arch/arm/nvidia/tegra_carreg.h
--- a/sys/arch/arm/nvidia/tegra_carreg.h        Sun May 03 11:46:44 2015 +0000
+++ b/sys/arch/arm/nvidia/tegra_carreg.h        Sun May 03 11:47:15 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_carreg.h,v 1.2 2015/05/02 14:10:03 jmcneill Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.3 2015/05/03 11:47:15 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -80,4 +80,17 @@
 #define CAR_RST_DEV_U_SET_REG          0x310
 #define CAR_RST_DEV_U_CLR_REG          0x314
 
+#define CAR_CLK_ENB_L_SET_REG          0x320
+#define CAR_CLK_ENB_L_CLR_REG          0x324
+#define CAR_CLK_ENB_H_SET_REG          0x328
+#define CAR_CLK_ENB_H_CLR_REG          0x32c
+#define CAR_CLK_ENB_U_SET_REG          0x330
+#define CAR_CLK_ENB_U_CLR_REG          0x334
+
+#define CAR_DEV_L_SDMMC4               __BIT(15)
+#define CAR_DEV_L_SDMMC1               __BIT(14)
+#define CAR_DEV_L_SDMMC2               __BIT(9)
+
+#define CAR_DEV_U_SDMMC3               __BIT(5)
+
 #endif /* _ARM_TEGRA_CARREG_H */