[src/trunk]: src/sys/arch/arm/cortex Make sure TLB is invalidated and ACTLR.S...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/924a7928d28a
branches:  trunk
changeset: 338231:924a7928d28a
user:      skrll <skrll%NetBSD.org@localhost>
date:      Fri May 15 10:57:55 2015 +0000

description:
Make sure TLB is invalidated and ACTLR.SMP is set on ARM A15.  ACTLR.SMP
enables the processor to receive instruction cache, BTB and TLB main-
tenance operations from other processors

diffstat:

 sys/arch/arm/cortex/a9_mpsubr.S |  10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diffs (38 lines):

diff -r 4efbf7483ef2 -r 924a7928d28a sys/arch/arm/cortex/a9_mpsubr.S
--- a/sys/arch/arm/cortex/a9_mpsubr.S   Fri May 15 10:53:58 2015 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S   Fri May 15 10:57:55 2015 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: a9_mpsubr.S,v 1.36 2015/05/03 16:18:51 matt Exp $      */
+/*     $NetBSD: a9_mpsubr.S,v 1.37 2015/05/15 10:57:55 skrll Exp $     */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -450,7 +450,7 @@
        XPUTC(#'2')
 #endif /* CORTEXA5 || CORTEXA9 */
 
-#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA17)
+#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
        //
        // The MMU is off.  Make sure the TLB is invalidated before
        // turning on SMP.
@@ -461,8 +461,8 @@
 
        // For the A7, SMP must be on ldrex/strex to work.
        //
-#if defined(MULTIPROCESSOR) || defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA17)
-#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA17)
+#if defined(MULTIPROCESSOR) || defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
+#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
        //
        // Step 4a, set ACTLR.SMP=1
        //
@@ -485,7 +485,7 @@
        mcr     p15, 0, r0, c1, c0, 1           // ACTLR write
        isb
        dsb
-#endif /* A5 || A7 || A9 || A17 */
+#endif /* A5 || A7 || A9 || A15 || A17 */
 #endif /* MULTIPROCESSOR */
 
        //