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[src/trunk]: src/sys/dev/marvell Switch to generic __BIT/__BITS macro, which ...
details: https://anonhg.NetBSD.org/src/rev/6faaa5256718
branches: trunk
changeset: 342950:6faaa5256718
user: joerg <joerg%NetBSD.org@localhost>
date: Fri Jan 15 12:09:15 2016 +0000
description:
Switch to generic __BIT/__BITS macro, which doesn't depend on
left-shifting negative values.
diffstat:
sys/dev/marvell/gtbrgreg.h | 31 +--
sys/dev/marvell/gtmpscreg.h | 287 +++++++++++++++++++++----------------------
sys/dev/marvell/gtsdmareg.h | 75 +++++------
3 files changed, 186 insertions(+), 207 deletions(-)
diffs (truncated from 611 to 300 lines):
diff -r 9281c476ce55 -r 6faaa5256718 sys/dev/marvell/gtbrgreg.h
--- a/sys/dev/marvell/gtbrgreg.h Fri Jan 15 09:05:16 2016 +0000
+++ b/sys/dev/marvell/gtbrgreg.h Fri Jan 15 12:09:15 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gtbrgreg.h,v 1.2 2010/04/28 13:51:56 kiyohara Exp $ */
+/* $NetBSD: gtbrgreg.h,v 1.3 2016/01/15 12:09:15 joerg Exp $ */
/*
* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
@@ -46,13 +46,6 @@
#ifndef _GTBRGREG_H
#define _GTBRGREG_H
-#ifndef BIT
-#define BIT(bitno) (1U << (bitno))
-#endif
-#ifndef BITS
-#define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
-#endif
-
#define GTBRG_NCHAN 3 /* Number of MPSC channels */
/*******************************************************************************
@@ -71,10 +64,10 @@
/*
* BRG Configuration Register bits
*/
-#define BRG_BCR_CDV BITS(15,0) /* Count Down Value */
-#define BRG_BCR_EN BIT(16) /* Enable BRG */
-#define BRG_BCR_RST BIT(17) /* Reset BRG */
-#define BRG_BCR_CLKS_MASK BITS(22,18) /* Clock Source */
+#define BRG_BCR_CDV __BITS(15,0) /* Count Down Value */
+#define BRG_BCR_EN __BIT(16) /* Enable BRG */
+#define BRG_BCR_RST __BIT(17) /* Reset BRG */
+#define BRG_BCR_CLKS_MASK __BITS(22,18) /* Clock Source */
#define BRG_BCR_CLKS_BCLKIN (0 << 18) /* from MPP */
#define BRG_BCR_CLKS_SCLK0 (2 << 18) /* from S0 port */
#define BRG_BCR_CLKS_TSCLK0 (3 << 18) /* from S0 port */
@@ -82,18 +75,18 @@
#define BRG_BCR_CLKS_TSCLK1 (7 << 18) /* from S1 port */
#define BRG_BCR_CLKS_TCLK (8 << 18) /* "Tclk" ??? */
/* all other values resvd. */
-#define BRG_BCR_RES BITS(31,23)
+#define BRG_BCR_RES __BITS(31,23)
/*
* BRG Baud Tuning Register bits
*/
-#define BRG_BTR_CUV BITS(15,0) /* Count Up Value */
-#define BRG_BTR_RES BITS(31,16)
+#define BRG_BTR_CUV __BITS(15,0) /* Count Up Value */
+#define BRG_BTR_RES __BITS(31,16)
/*
* BRG Cause and Mask interrupt Register bits
*/
-#define BRG_INTR_BTR0 BIT(0) /* Baud Tuning 0 irpt. */
-#define BRG_INTR_BTR1 BIT(1) /* Baud Tuning 1 irpt. */
-#define BRG_INTR_BTR2 BIT(2) /* Baud Tuning 2 irpt. */
-#define BRG_INTR_RES BITS(31,3)
+#define BRG_INTR_BTR0 __BIT(0) /* Baud Tuning 0 irpt. */
+#define BRG_INTR_BTR1 __BIT(1) /* Baud Tuning 1 irpt. */
+#define BRG_INTR_BTR2 __BIT(2) /* Baud Tuning 2 irpt. */
+#define BRG_INTR_RES __BITS(31,3)
#endif /* _GTBRGREG_H */
diff -r 9281c476ce55 -r 6faaa5256718 sys/dev/marvell/gtmpscreg.h
--- a/sys/dev/marvell/gtmpscreg.h Fri Jan 15 09:05:16 2016 +0000
+++ b/sys/dev/marvell/gtmpscreg.h Fri Jan 15 12:09:15 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gtmpscreg.h,v 1.4 2010/04/28 13:51:56 kiyohara Exp $ */
+/* $NetBSD: gtmpscreg.h,v 1.5 2016/01/15 12:09:15 joerg Exp $ */
/*
* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
@@ -46,13 +46,6 @@
#ifndef _GTMPSCREG_H
#define _GTMPSCREG_H
-#ifndef BIT
-#define BIT(bitno) (1U << (bitno))
-#endif
-#ifndef BITS
-#define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
-#endif
-
#define GTMPSC_BASE(u) (MPSC0_BASE + ((u) << 12))
#define GTMPSC_SIZE 0x1000
@@ -86,11 +79,11 @@
#define GTMPSC_MRR_PORT0 0 /* serial port #0 */
#define GTMPSC_MRR_NONE 7 /* unconnected */
/* all other "routes" resvd. */
-#define GTMPSC_MRR_MR0_MASK BITS(2,0) /* routing mask for MPSC0 */
-#define GTMPSC_MRR_RESa BITS(5,3)
-#define GTMPSC_MRR_MR1_MASK BITS(8,6) /* routing mask for MPSC1 */
-#define GTMPSC_MRR_RESb BITS(30,9)
-#define GTMPSC_MRRE_DSC BIT(31) /* "Don't Stop Clock" */
+#define GTMPSC_MRR_MR0_MASK __BITS(2,0) /* routing mask for MPSC0 */
+#define GTMPSC_MRR_RESa __BITS(5,3)
+#define GTMPSC_MRR_MR1_MASK __BITS(8,6) /* routing mask for MPSC1 */
+#define GTMPSC_MRR_RESb __BITS(30,9)
+#define GTMPSC_MRRE_DSC __BIT(31) /* "Don't Stop Clock" */
#define GTMPSC_MRR_RES (GTMPSC_MRR_RESa|GTMPSC_MRR_RESb)
/*
* MPSC Clock Routing Register bits
@@ -106,92 +99,92 @@
#define GTMPSC_CRR(u, v) ((v) << GTMPSC_CRR_SHIFT(u))
#define GTMPSC_CRR_SHIFT(u) ((u) * 8)
#define GTMPSC_CRR_MASK 0xf
-#define GTMPSC_CRR_RESa BITS(7,4)
-#define GTMPSC_CRR_RESb BITS(31,12)
+#define GTMPSC_CRR_RESa __BITS(7,4)
+#define GTMPSC_CRR_RESb __BITS(31,12)
#define GTMPSC_CRR_RES (GTMPSC_CRR_RESa|GTMPSC_CRR_RESb)
/*
* MPSC Main Configuration Register LO bits
*/
-#define GTMPSC_MMCR_LO_MODE_MASK BITS(2,0)
+#define GTMPSC_MMCR_LO_MODE_MASK __BITS(2,0)
#define GTMPSC_MMCR_LO_MODE_UART (0x4 << 0) /* UART mode */
-#define GTMPSC_MMCR_LO_TTX BIT(3) /* Transparent TX */
-#define GTMPSC_MMCR_LO_TRX BIT(4) /* Transparent RX */
-#define GTMPSC_MMCR_LO_RESa BIT(5)
-#define GTMPSC_MMCR_LO_ET BIT(6) /* Enable TX */
-#define GTMPSC_MMCR_LO_ER BIT(7) /* Enable RX */
-#define GTMPSC_MMCR_LO_LPBK_MASK BITS(9,8) /* Loop Back */
+#define GTMPSC_MMCR_LO_TTX __BIT(3) /* Transparent TX */
+#define GTMPSC_MMCR_LO_TRX __BIT(4) /* Transparent RX */
+#define GTMPSC_MMCR_LO_RESa __BIT(5)
+#define GTMPSC_MMCR_LO_ET __BIT(6) /* Enable TX */
+#define GTMPSC_MMCR_LO_ER __BIT(7) /* Enable RX */
+#define GTMPSC_MMCR_LO_LPBK_MASK __BITS(9,8) /* Loop Back */
#define GTMPSC_MMCR_LO_LPBK_NONE (0 << 8) /* Normal (non-loop) */
#define GTMPSC_MMCR_LO_LPBK_LOOP (1 << 8) /* Loop Back */
#define GTMPSC_MMCR_LO_LPBK_ECHO (2 << 8) /* Echo */
#define GTMPSC_MMCR_LO_LPBK_LBE (3 << 8) /* Loop Back and Echo */
-#define GTMPSC_MMCR_LO_NLM BIT(10) /* Null Modem */
-#define GTMPSC_MMCR_LO_RESb BIT(11)
-#define GTMPSC_MMCR_LO_TSYN BIT(12) /* Transmitter sync to Rcvr. */
-#define GTMPSC_MMCR_LO_RESc BIT(13)
-#define GTMPSC_MMCR_LO_TSNS_MASK BITS(15,14) /* Transmit Sense */
+#define GTMPSC_MMCR_LO_NLM __BIT(10) /* Null Modem */
+#define GTMPSC_MMCR_LO_RESb __BIT(11)
+#define GTMPSC_MMCR_LO_TSYN __BIT(12) /* Transmitter sync to Rcvr. */
+#define GTMPSC_MMCR_LO_RESc __BIT(13)
+#define GTMPSC_MMCR_LO_TSNS_MASK __BITS(15,14) /* Transmit Sense */
#define GTMPSC_MMCR_LO_TSNS_INF (0 << 14) /* Infinite */
-#define GTMPSC_MMCR_LO_TIDL BIT(16) /* TX Idles */
-#define GTMPSC_MMCR_LO_RTSM BIT(17) /* RTS Mode */
-#define GTMPSC_MMCR_LO_RESd BIT(18)
-#define GTMPSC_MMCR_LO_CTSS BIT(19) /* CTS Sampling mode */
-#define GTMPSC_MMCR_LO_CDS BIT(20) /* CD Sampling mode */
-#define GTMPSC_MMCR_LO_CTSM BIT(21) /* CTS operating Mode */
-#define GTMPSC_MMCR_LO_CDM BIT(22) /* CD operating Mode */
-#define GTMPSC_MMCR_LO_CRCM_MASK BITS(25,23) /* CRC Mode */
+#define GTMPSC_MMCR_LO_TIDL __BIT(16) /* TX Idles */
+#define GTMPSC_MMCR_LO_RTSM __BIT(17) /* RTS Mode */
+#define GTMPSC_MMCR_LO_RESd __BIT(18)
+#define GTMPSC_MMCR_LO_CTSS __BIT(19) /* CTS Sampling mode */
+#define GTMPSC_MMCR_LO_CDS __BIT(20) /* CD Sampling mode */
+#define GTMPSC_MMCR_LO_CTSM __BIT(21) /* CTS operating Mode */
+#define GTMPSC_MMCR_LO_CDM __BIT(22) /* CD operating Mode */
+#define GTMPSC_MMCR_LO_CRCM_MASK __BITS(25,23) /* CRC Mode */
#define GTMPSC_MMCR_LO_CRCM_NONE (0 << 23) /* CRC Mode */
-#define GTMPSC_MMCR_LO_RESe BITS(27,26)
-#define GTMPSC_MMCR_LO_TRVD BIT(28) /* Transmit Reverse Data */
-#define GTMPSC_MMCR_LO_RRVD BIT(29) /* Receive Reverse Data */
-#define GTMPSC_MMCR_LO_RESf BIT(30)
-#define GTMPSC_MMCR_LO_GDE BIT(31) /* Glitch Detect Enable */
+#define GTMPSC_MMCR_LO_RESe __BITS(27,26)
+#define GTMPSC_MMCR_LO_TRVD __BIT(28) /* Transmit Reverse Data */
+#define GTMPSC_MMCR_LO_RRVD __BIT(29) /* Receive Reverse Data */
+#define GTMPSC_MMCR_LO_RESf __BIT(30)
+#define GTMPSC_MMCR_LO_GDE __BIT(31) /* Glitch Detect Enable */
#define GTMPSC_MMCR_LO_RES \
(GTMPSC_MMCR_LO_RESa|GTMPSC_MMCR_LO_RESb|GTMPSC_MMCR_LO_RESc \
|GTMPSC_MMCR_LO_RESd|GTMPSC_MMCR_LO_RESe|GTMPSC_MMCR_LO_RESf)
/*
* MPSC Main Configuration Register HI bits
*/
-#define GTMPSC_MMCR_HI_TCI BIT(0) /* TX Clock Invert */
-#define GTMPSC_MMCR_HI_TINV BIT(1) /* TX Bitstream Inversion */
-#define GTMPSC_MMCR_HI_TPL BITS(4,2) /* TX Preable Length */
+#define GTMPSC_MMCR_HI_TCI __BIT(0) /* TX Clock Invert */
+#define GTMPSC_MMCR_HI_TINV __BIT(1) /* TX Bitstream Inversion */
+#define GTMPSC_MMCR_HI_TPL __BITS(4,2) /* TX Preable Length */
#define GTMPSC_MMCR_HI_TPL_NONE 0 /* no TX Preable (default) */
#define GTMPSC_MMCR_HI_TPL_16 (6 << 2) /* 16 byte preamble */
-#define GTMPSC_MMCR_HI_TPPT_MASK BITS(8,5) /* TX Preable Pattern */
+#define GTMPSC_MMCR_HI_TPPT_MASK __BITS(8,5) /* TX Preable Pattern */
#define GTMPSC_MMCR_HI_TPPT_NONE (0 << 5) /* TX Preable Pattern */
-#define GTMPSC_MMCR_HI_TCDV_MASK BITS(10,9) /* TX Clock Divide */
+#define GTMPSC_MMCR_HI_TCDV_MASK __BITS(10,9) /* TX Clock Divide */
#define GTMPSC_MMCR_HI_TCDV_1X (0 << 9) /* 1x clock mode */
#define GTMPSC_MMCR_HI_TCDV_8X (1 << 9) /* 8x clock mode */
#define GTMPSC_MMCR_HI_TCDV_16X (2 << 9) /* 16x clock mode */
#define GTMPSC_MMCR_HI_TCDV_32X (3 << 9) /* 32x clock mode */
-#define GTMPSC_MMCR_HI_TDEC_MASK BITS(13,11) /* TX Encoder */
+#define GTMPSC_MMCR_HI_TDEC_MASK __BITS(13,11) /* TX Encoder */
#define GTMPSC_MMCR_HI_TDEC_NRZ (0 << 9) /* NRZ (default) */
#define GTMPSC_MMCR_HI_TDEC_NRZI (1 << 9) /* NRZI (mark) */
#define GTMPSC_MMCR_HI_TDEC_FM0 (2 << 9) /* FM0 */
#define GTMPSC_MMCR_HI_TDEC_MAN (4 << 9) /* Manchester */
#define GTMPSC_MMCR_HI_TDEC_DMAN (6 << 9) /* Differential Manchester */
/* all other values rsvd. */
-#define GTMPSC_MMCR_HI_RESa BITS(15,14)
-#define GTMPSC_MMCR_HI_RINV BIT(16) /* RX Bitstream Inversion */
-#define GTMPSC_MMCR_HI_GDW BITS(20,17) /* Clock Glitch Width */
-#define GTMPSC_MMCR_HI_RESb BIT(21)
-#define GTMPSC_MMCR_HI_RDW BIT(22) /* Reveive Data Width */
-#define GTMPSC_MMCR_HI_RSYL_MASK BITS(24,23) /* Reveive Sync Width */
+#define GTMPSC_MMCR_HI_RESa __BITS(15,14)
+#define GTMPSC_MMCR_HI_RINV __BIT(16) /* RX Bitstream Inversion */
+#define GTMPSC_MMCR_HI_GDW __BITS(20,17) /* Clock Glitch Width */
+#define GTMPSC_MMCR_HI_RESb __BIT(21)
+#define GTMPSC_MMCR_HI_RDW __BIT(22) /* Reveive Data Width */
+#define GTMPSC_MMCR_HI_RSYL_MASK __BITS(24,23) /* Reveive Sync Width */
#define GTMPSC_MMCR_HI_RSYL_EXT (0 << 23) /* External sync */
#define GTMPSC_MMCR_HI_RSYL_4BIT (1 << 23) /* 4-bit sync */
#define GTMPSC_MMCR_HI_RSYL_8BIT (2 << 23) /* 8-bit sync */
#define GTMPSC_MMCR_HI_RSYL_16BIT (3 << 23) /* 16-bit sync */
-#define GTMPSC_MMCR_HI_RCDV_MASK BITS(26,25) /* Receive Clock Divider */
+#define GTMPSC_MMCR_HI_RCDV_MASK __BITS(26,25) /* Receive Clock Divider */
#define GTMPSC_MMCR_HI_RCDV_1X (0 << 25) /* 1x clock mode (default) */
#define GTMPSC_MMCR_HI_RCDV_8X (1 << 25) /* 8x clock mode (default) */
#define GTMPSC_MMCR_HI_RCDV_16X (2 << 25) /* 16x clock mode (default) */
#define GTMPSC_MMCR_HI_RCDV_32X (3 << 25) /* 16x clock mode (default) */
-#define GTMPSC_MMCR_HI_RENC_MASK BITS(29,27) /* Receive Encoder */
+#define GTMPSC_MMCR_HI_RENC_MASK __BITS(29,27) /* Receive Encoder */
#define GTMPSC_MMCR_HI_RENC_NRZ (0 << 27) /* NRZ (default) */
#define GTMPSC_MMCR_HI_RENC_NRZI (1 << 27) /* NRZI */
#define GTMPSC_MMCR_HI_RENC_FM0 (2 << 27) /* FM0 */
#define GTMPSC_MMCR_HI_RENC_MAN (4 << 27) /* Manchester */
#define GTMPSC_MMCR_HI_RENC_DMAN (6 << 27) /* Differential Manchester */
/* all other values rsvd. */
-#define GTMPSC_MMCR_HI_SEDG_MASK BITS(31,30) /* Sync Clock Edge */
+#define GTMPSC_MMCR_HI_SEDG_MASK __BITS(31,30) /* Sync Clock Edge */
#define GTMPSC_MMCR_HI_SEDG_BOTH (0 << 30) /* rising and falling (dflt) */
#define GTMPSC_MMCR_HI_SEDG_RISE (1 << 30) /* rising edge */
#define GTMPSC_MMCR_HI_SEDG_FALL (2 << 30) /* falling edge */
@@ -201,61 +194,61 @@
*
* XXX these belong in sdmareg.h ?
*/
-#define SDMA_CSR_RX_PE BIT(0) /* Parity Error */
-#define SDMA_CSR_RX_CDL BIT(1) /* Carrier Detect Loss */
-#define SDMA_CSR_RX_RESa BIT(2)
-#define SDMA_CSR_RX_FR BIT(3) /* Framing Error */
-#define SDMA_CSR_RX_RESb BITS(5,4)
-#define SDMA_CSR_RX_OR BIT(6) /* Data Overrun */
-#define SDMA_CSR_RX_RESc BITS(8,7)
-#define SDMA_CSR_RX_BR BIT(9) /* Break Received */
-#define SDMA_CSR_RX_MI BIT(10) /* Max Idle */
-#define SDMA_CSR_RX_ADDR BIT(11) /* Address */
-#define SDMA_CSR_RX_AMATCH BIT(12) /* Address match */
-#define SDMA_CSR_RX_CT BIT(13) /* Transparency Control char */
-#define SDMA_CSR_RX_C BIT(14) /* Control char */
-#define SDMA_CSR_RX_ES BIT(15) /* Error Summary */
-#define SDMA_CSR_RX_L BIT(16) /* Last */
-#define SDMA_CSR_RX_F BIT(17) /* First */
-#define SDMA_CSR_RX_RESd BITS(22,18)
-#define SDMA_CSR_RX_EI BIT(23) /* Enable Interrupt */
-#define SDMA_CSR_RX_RESe BITS(29,24)
-#define SDMA_CSR_RX_AUTO BIT(30) /* Auto Mode */
-#define SDMA_CSR_RX_OWN BIT(31) /* Owner */
+#define SDMA_CSR_RX_PE __BIT(0) /* Parity Error */
+#define SDMA_CSR_RX_CDL __BIT(1) /* Carrier Detect Loss */
+#define SDMA_CSR_RX_RESa __BIT(2)
+#define SDMA_CSR_RX_FR __BIT(3) /* Framing Error */
+#define SDMA_CSR_RX_RESb __BITS(5,4)
+#define SDMA_CSR_RX_OR __BIT(6) /* Data Overrun */
+#define SDMA_CSR_RX_RESc __BITS(8,7)
+#define SDMA_CSR_RX_BR __BIT(9) /* Break Received */
+#define SDMA_CSR_RX_MI __BIT(10) /* Max Idle */
+#define SDMA_CSR_RX_ADDR __BIT(11) /* Address */
+#define SDMA_CSR_RX_AMATCH __BIT(12) /* Address match */
+#define SDMA_CSR_RX_CT __BIT(13) /* Transparency Control char */
+#define SDMA_CSR_RX_C __BIT(14) /* Control char */
+#define SDMA_CSR_RX_ES __BIT(15) /* Error Summary */
+#define SDMA_CSR_RX_L __BIT(16) /* Last */
+#define SDMA_CSR_RX_F __BIT(17) /* First */
+#define SDMA_CSR_RX_RESd __BITS(22,18)
+#define SDMA_CSR_RX_EI __BIT(23) /* Enable Interrupt */
+#define SDMA_CSR_RX_RESe __BITS(29,24)
+#define SDMA_CSR_RX_AUTO __BIT(30) /* Auto Mode */
+#define SDMA_CSR_RX_OWN __BIT(31) /* Owner */
#define SDMA_CSR_RX_RES (SDMA_CSR_RX_RESa|SDMA_CSR_RX_RESb|SDMA_CSR_RX_RESc \
|SDMA_CSR_RX_RESd|SDMA_CSR_RX_RESe)
/*
* SDMAx Command/Status Register bits for UART Mode, TX
*/
-#define SDMA_CSR_TX_RESa BIT(0)
-#define SDMA_CSR_TX_CTSL BIT(1) /* CTS Loss */
-#define SDMA_CSR_TX_RESb BITS(14,2)
-#define SDMA_CSR_TX_ES BIT(15) /* Error Summary */
-#define SDMA_CSR_TX_L BIT(16) /* Last */
-#define SDMA_CSR_TX_F BIT(17) /* First */
-#define SDMA_CSR_TX_P BIT(18) /* Preamble */
-#define SDMA_CSR_TX_ADDR BIT(19) /* Address */
-#define SDMA_CSR_TX_NS BIT(20) /* No Stop Bit */
-#define SDMA_CSR_TX_RESc BITS(22,21)
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