Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/evbmips first shot at SMP support, very much broken...
details: https://anonhg.NetBSD.org/src/rev/16270cbe4d69
branches: trunk
changeset: 343299:16270cbe4d69
user: macallan <macallan%NetBSD.org@localhost>
date: Fri Jan 29 01:54:13 2016 +0000
description:
first shot at SMP support, very much broken and experimental
So far the 2nd core wakes up, makes its way to the idle loop, and things lock
up when we start the timer interrupt.
diffstat:
sys/arch/evbmips/conf/CI20 | 6 +-
sys/arch/evbmips/conf/files.ingenic | 5 +-
sys/arch/evbmips/ingenic/clock.c | 18 +++-
sys/arch/evbmips/ingenic/cpu.c | 122 ++++++++++++++++++++++++++++++
sys/arch/evbmips/ingenic/cpu_startup.S | 130 +++++++++++++++++++++++++++++++++
sys/arch/evbmips/ingenic/intr.c | 32 ++++++-
sys/arch/evbmips/ingenic/machdep.c | 16 +++-
sys/arch/evbmips/ingenic/mainbus.c | 10 +-
8 files changed, 317 insertions(+), 22 deletions(-)
diffs (truncated from 584 to 300 lines):
diff -r 2b216757fad5 -r 16270cbe4d69 sys/arch/evbmips/conf/CI20
--- a/sys/arch/evbmips/conf/CI20 Thu Jan 28 23:50:04 2016 +0000
+++ b/sys/arch/evbmips/conf/CI20 Fri Jan 29 01:54:13 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: CI20,v 1.20 2016/01/03 06:23:25 macallan Exp $
+# $NetBSD: CI20,v 1.21 2016/01/29 01:54:13 macallan Exp $
#
# MIPS Creator CI20
#
@@ -7,7 +7,7 @@
#options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "CI20-$Revision: 1.20 $"
+#ident "CI20-$Revision: 1.21 $"
maxusers 32
@@ -138,7 +138,7 @@
mainbus0 at root
#options MULTIPROCESSOR
-cpu0 at mainbus?
+cpu* at mainbus?
#wdog0 at mainbus?
apbus0 at mainbus?
diff -r 2b216757fad5 -r 16270cbe4d69 sys/arch/evbmips/conf/files.ingenic
--- a/sys/arch/evbmips/conf/files.ingenic Thu Jan 28 23:50:04 2016 +0000
+++ b/sys/arch/evbmips/conf/files.ingenic Fri Jan 29 01:54:13 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.ingenic,v 1.5 2014/12/26 17:45:27 macallan Exp $
+# $NetBSD: files.ingenic,v 1.6 2016/01/29 01:54:13 macallan Exp $
file arch/mips/mips/bus_dma.c
@@ -12,6 +12,7 @@
file arch/evbmips/ingenic/machdep.c
file arch/evbmips/ingenic/intr.c
file arch/evbmips/ingenic/clock.c
+file arch/evbmips/ingenic/cpu_startup.S
# System bus
device mainbus { }
@@ -20,7 +21,7 @@
device cpu
attach cpu at mainbus
-file arch/evbmips/evbmips/cpu.c cpu
+file arch/evbmips/ingenic/cpu.c cpu
# Memory Disk
file dev/md_root.c memory_disk_hooks
diff -r 2b216757fad5 -r 16270cbe4d69 sys/arch/evbmips/ingenic/clock.c
--- a/sys/arch/evbmips/ingenic/clock.c Thu Jan 28 23:50:04 2016 +0000
+++ b/sys/arch/evbmips/ingenic/clock.c Fri Jan 29 01:54:13 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: clock.c,v 1.6 2015/06/30 04:10:10 macallan Exp $ */
+/* $NetBSD: clock.c,v 1.7 2016/01/29 01:54:14 macallan Exp $ */
/*-
* Copyright (c) 2014 Michael Lorenz
@@ -27,7 +27,9 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.6 2015/06/30 04:10:10 macallan Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.7 2016/01/29 01:54:14 macallan Exp $");
+
+#include "opt_multiprocessor.h"
#include <sys/param.h>
#include <sys/cpu.h>
@@ -130,6 +132,8 @@
printf("INTC %08x %08x\n", readreg(JZ_ICSR0), readreg(JZ_ICSR1));
delay(3000000);
+ printf("%s %d\n", __func__, MFC0(12, 3));
+ printf("%s %08x\n", __func__, MFC0(12, 4));
#endif
}
@@ -190,6 +194,7 @@
ingenic_clockintr(uint32_t id)
{
extern struct clockframe cf;
+ int s = splsched();
struct cpu_info * const ci = curcpu();
#ifdef USE_OST
uint32_t new_cnt;
@@ -198,7 +203,6 @@
/* clear flags */
writereg(JZ_TC_TFCR, TFR_OSTFLAG);
- KASSERT((ci->ci_cycles_per_hz & ~(0xffffffff)) == 0);
ci->ci_next_cp0_clk_intr += (uint32_t)(ci->ci_cycles_per_hz & 0xffffffff);
#ifdef USE_OST
writereg(JZ_OST_DATA, ci->ci_next_cp0_clk_intr);
@@ -228,5 +232,13 @@
ingenic_puts("+");
}
#endif
+#ifdef MULTIPROCESSOR
+ /*
+ * XXX
+ * needs to take the IPI lock and ping all online CPUs, not just core 1
+ */
+ MTC0(1 << IPI_CLOCK, 20, 1);
+#endif
hardclock(&cf);
+ splx(s);
}
diff -r 2b216757fad5 -r 16270cbe4d69 sys/arch/evbmips/ingenic/cpu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/evbmips/ingenic/cpu.c Fri Jan 29 01:54:13 2016 +0000
@@ -0,0 +1,122 @@
+/* $NetBSD: cpu.c,v 1.1 2016/01/29 01:54:14 macallan Exp $ */
+
+/*
+ * Copyright 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Simon Burge for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.1 2016/01/29 01:54:14 macallan Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+#include <sys/cpu.h>
+
+#include <mips/locore.h>
+#include <mips/asm.h>
+#include <mips/ingenic/ingenic_regs.h>
+
+#include "opt_ingenic.h"
+
+static int cpu_match(device_t, cfdata_t, void *);
+static void cpu_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(cpu, 0,
+ cpu_match, cpu_attach, NULL, NULL);
+
+struct cpu_info *startup_cpu_info;
+extern void *ingenic_wakeup;
+
+static int
+cpu_match(device_t parent, cfdata_t match, void *aux)
+{
+ struct mainbusdev {
+ const char *md_name;
+ } *aa = aux;
+ if (strcmp(aa->md_name, "cpu") == 0) return 1;
+ return 0;
+}
+
+static void
+cpu_attach(device_t parent, device_t self, void *aux)
+{
+ struct cpu_info *ci = curcpu();
+ int unit;
+
+ if ((unit = device_unit(self)) > 0) {
+#ifdef MULTIPROCESSOR
+ uint32_t vec, reg;
+ int bail = 10000;
+
+ startup_cpu_info = cpu_info_alloc(NULL, unit, 0, unit, 0);
+ startup_cpu_info->ci_cpu_freq = ci->ci_cpu_freq;
+ ci = startup_cpu_info;
+ wbflush();
+ vec = (uint32_t)&ingenic_wakeup;
+ reg = MFC0(12, 4); /* reset entry reg */
+ reg &= ~REIM_ENTRY_M;
+ reg |= vec;
+ MTC0(reg, 12, 4);
+ reg = MFC0(12, 2); /* core control reg */
+ reg |= CC_RPC1; /* use our exception vector */
+ reg &= ~CC_SW_RST1; /* get core 1 out of reset */
+ MTC0(reg, 12, 2);
+ while ((!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) && (bail > 0)) {
+ delay(1000);
+ bail--;
+ }
+ if (!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) {
+ aprint_error_dev(self, "did not hatch\n");
+ return;
+ }
+#else
+ aprint_normal_dev(self,
+ "processor off-line; "
+ "multiprocessor support not present in kernel\n");
+ return;
+#endif
+
+ }
+ ci->ci_dev = self;
+ self->dv_private = ci;
+
+ aprint_normal(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n",
+ ci->ci_cpu_freq / 1000000,
+ (ci->ci_cpu_freq % 1000000) / 10000,
+ ci->ci_cycles_per_hz, ci->ci_divisor_delay);
+
+ aprint_normal_dev(self, "");
+ cpu_identify(self);
+ cpu_attach_common(self, ci);
+}
diff -r 2b216757fad5 -r 16270cbe4d69 sys/arch/evbmips/ingenic/cpu_startup.S
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/evbmips/ingenic/cpu_startup.S Fri Jan 29 01:54:13 2016 +0000
@@ -0,0 +1,130 @@
+/* $NetBSD: cpu_startup.S,v 1.1 2016/01/29 01:54:14 macallan Exp $ */
+
+/*-
+ * Copyright (c) 2015 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "opt_cputype.h"
+#include "opt_multiprocessor.h"
+
+#include <sys/cdefs.h>
+#include <sys/endian.h>
+
+#include <mips/asm.h>
+RCSID("$NetBSD: cpu_startup.S,v 1.1 2016/01/29 01:54:14 macallan Exp $");
+
+#ifdef MULTIPROCESSOR
+
+#include <mips/cpuregs.h>
+#include <mips/cache_r4k.h>
+
+#include "assym.h"
+
+#define CACHE_SIZE (32 * 1024)
+#define CACHE_LINESIZE 32
+
+NESTED_NOPROFILE(ingenic_trampoline, 0, ra)
+ /*
+ * We act as the idle lwp so make it CURLWP. When know
+ * that the cpu_info is a KSEG0 address.
+ */
+ move a0, a1
+ // Loop until idlelwp is filled in.
+1: PTR_L MIPS_CURLWP, CPU_INFO_IDLELWP(a0)
+ nop
+ beqz MIPS_CURLWP, 1b
+ nop
Home |
Main Index |
Thread Index |
Old Index