[src/trunk]: src/sys/dev/ic add defines for dataset management (from NVMe spe...

[jdolecek <jdolecek%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9201297b8014
branches:  trunk
changeset: 348188:9201297b8014
user:      jdolecek <jdolecek%NetBSD.org@localhost>
date:      Sat Oct 08 16:05:32 2016 +0000

description:
add defines for dataset management (from NVMe spec rev 1.2)

diffstat:

 sys/dev/ic/nvmereg.h |  21 +++++++++++++++++++--
 1 files changed, 19 insertions(+), 2 deletions(-)

diffs (38 lines):

diff -r 4ba50ab4fe3b -r 9201297b8014 sys/dev/ic/nvmereg.h
--- a/sys/dev/ic/nvmereg.h      Sat Oct 08 15:57:11 2016 +0000
+++ b/sys/dev/ic/nvmereg.h      Sat Oct 08 16:05:32 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: nvmereg.h,v 1.5 2016/09/17 23:59:30 jdolecek Exp $     */
+/*     $NetBSD: nvmereg.h,v 1.6 2016/10/08 16:05:32 jdolecek Exp $     */
 /*     $OpenBSD: nvmereg.h,v 1.10 2016/04/14 11:18:32 dlg Exp $ */
 
 /*
@@ -188,10 +188,27 @@
 
        uint16_t        nlb;    /* Number of Logical Blocks */
        uint16_t        ioflags;
+#define NVM_SQE_IO_LR  __BIT(15)       /* Limited Retry */
 #define NVM_SQE_IO_FUA __BIT(14)       /* Force Unit Access (bypass cache) */
-#define NVM_SQE_IO_LR  __BIT(15)       /* Limited Retry */
 
        uint8_t         dsm;    /* Dataset Management */
+#define NVM_SQE_IO_INCOMP      __BIT(7)        /* Incompressible */
+#define NVM_SQE_IO_SEQ         __BIT(6)        /* Sequential request */
+#define NVM_SQE_IO_LAT_MASK    __BITS(4, 5)    /* Access Latency */
+#define  NVM_SQE_IO_LAT_NONE   0               /* Latency: none */
+#define  NVM_SQE_IO_LAT_IDLE   __BIT(4)        /* Latency: idle */
+#define  NVM_SQE_IO_LAT_NORMAL __BIT(5)        /* Latency: normal */
+#define  NVM_SQE_IO_LAT_LOW    __BITS(4, 5)    /* Latency: low */
+#define NVM_SQE_IO_FREQ_MASK   __BITS(0, 3)    /* Access Frequency */
+#define  NVM_SQE_IO_FREQ_TYPICAL       0x1     /* Typical */
+#define  NVM_SQE_IO_FREQ_INFR_INFW     0x2     /* Infrequent read and writes */
+#define  NVM_SQE_IO_FREQ_FRR_INFW      0x3     /* Frequent read, inf. writes */
+#define  NVM_SQE_IO_FREQ_INFR_FRW      0x4     /* Inf. read, freq. writes */
+#define  NVM_SQE_IO_FREQ_FRR_FRW       0x5     /* Freq. read and writes */
+#define  NVM_SQE_IO_FREQ_ONCE          0x6     /* One time i/o operation */
+/* Extra Access Frequency bits for read operations */
+#define  NVM_SQE_IO_FREQ_SPEC          0x7     /* Speculative read - prefech */
+#define  NVM_SQE_IO_FREQ_OVERWRITE     0x8     /* Will be overwritten soon */
        uint8_t         _reserved2[3];
 
        uint32_t        eilbrt; /* Expected Initial Logical Block