[src/trunk]: src/sys/dev/pci - pci_conf_print_pwrbdgt_base_power(): From 0xf3...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/32013b149514
branches:  trunk
changeset: 348478:32013b149514
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Thu Oct 20 04:11:02 2016 +0000

description:
- pci_conf_print_pwrbdgt_base_power(): From 0xf3 to 0xff of the Base power are
  reserved above 300W (PCI 3.0 Errata).
- Emergency Power Reduction mechanism with PWRBRK signal ECN.
- Extended Message Data for MSI ECN.
- Fix typo in comment.

diffstat:

 sys/dev/pci/pci_subr.c |  37 ++++++++++++++++++++++++++++++++++---
 sys/dev/pci/pcireg.h   |  10 ++++++++--
 2 files changed, 42 insertions(+), 5 deletions(-)

diffs (139 lines):

diff -r 888e69c2aadc -r 32013b149514 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c    Thu Oct 20 04:06:53 2016 +0000
+++ b/sys/dev/pci/pci_subr.c    Thu Oct 20 04:11:02 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci_subr.c,v 1.151 2016/10/19 04:23:37 msaitoh Exp $   */
+/*     $NetBSD: pci_subr.c,v 1.152 2016/10/20 04:11:02 msaitoh Exp $   */
 
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
@@ -40,7 +40,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.151 2016/10/19 04:23:37 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.152 2016/10/20 04:11:02 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -1080,6 +1080,8 @@
            mme > 0 ? "on" : "off", 1 << mme, mme > 0 ? "s" : "");
        onoff("64 Bit Address Capable", ctl, PCI_MSI_CTL_64BIT_ADDR);
        onoff("Per-Vector Masking Capable", ctl, PCI_MSI_CTL_PERVEC_MASK);
+       onoff("Extended Message Data Capable", ctl, PCI_MSI_CTL_EXTMDATA_CAP);
+       onoff("Extended Message Data Enable", ctl, PCI_MSI_CTL_EXTMDATA_EN);
        printf("    Message Address %sregister: 0x%08x\n",
            ctl & PCI_MSI_CTL_64BIT_ADDR ? "(lower) " : "", *regs++);
        if (ctl & PCI_MSI_CTL_64BIT_ADDR) {
@@ -1594,6 +1596,8 @@
        onoff("Unsupported Request Detected", reg, PCIE_DCSR_URD);
        onoff("Aux Power Detected", reg, PCIE_DCSR_AUX_PWR);
        onoff("Transaction Pending", reg, PCIE_DCSR_TRANSACTION_PND);
+       onoff("Emergency Power Reduction Detected", reg,
+           PCIE_DCSR_EMGPWRREDD);
 
        if (check_link) {
                /* Link Capability Register */
@@ -1862,6 +1866,23 @@
        onoff("End-End TLP Prefix Supported", reg, PCIE_DCAP2_EETLP_PREF);
        printf("      Max End-End TLP Prefixes: %u\n",
            (unsigned int)(reg & PCIE_DCAP2_MAX_EETLP) >> 22);
+       printf("      Emergency Power Reduction Supported: ");
+       switch (__SHIFTOUT(reg, PCIE_DCAP2_EMGPWRRED)) {
+       case 0x0:
+               printf("Not supported\n");
+               break;
+       case 0x1:
+               printf("Device Specific mechanism\n");
+               break;
+       case 0x2:
+               printf("Form Factor spec or Device Specific mechanism\n");
+               break;
+       case 0x3:
+               printf("Reserved\n");
+               break;
+       }
+       onoff("Emergency Power Reduction Initialization Required", reg,
+           PCIE_DCAP2_EMGPWRRED_INI);
        onoff("FRS Supported", reg, PCIE_DCAP2_FRS);
 
        /* Device Control 2 */
@@ -1876,6 +1897,8 @@
        onoff("IDO Request Enabled", reg, PCIE_DCSR2_IDO_REQ);
        onoff("IDO Completion Enabled", reg, PCIE_DCSR2_IDO_COMP);
        onoff("LTR Mechanism Enabled", reg, PCIE_DCSR2_LTR_MEC);
+       onoff("Emergency Power Reduction Request", reg,
+           PCIE_DCSR2_EMGPWRRED_REQ);
        printf("      OBFF: ");
        switch ((reg & PCIE_DCSR2_OBFF_EN) >> 13) {
        case 0x0:
@@ -2478,8 +2501,12 @@
        case 0xf2:
                return "275W < x <= 300W";
        default:
-               return "Unknown";
+               break;
        }
+       if (reg >= 0xf3)
+               return "reserved for above 300W";
+
+       return "Unknown";
 }
 
 static const char *
@@ -2513,6 +2540,10 @@
                return "Idle";
        case 0x03:
                return "Sustained";
+       case 0x04:
+               return "Sustained (Emergency Power Reduction)";
+       case 0x05:
+               return "Maximum (Emergency Power Reduction)";
        case 0x07:
                return "Maximun";
        default:
diff -r 888e69c2aadc -r 32013b149514 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Thu Oct 20 04:06:53 2016 +0000
+++ b/sys/dev/pci/pcireg.h      Thu Oct 20 04:11:02 2016 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.115 2016/10/19 04:23:37 msaitoh Exp $     */
+/*     $NetBSD: pcireg.h,v 1.116 2016/10/20 04:11:02 msaitoh Exp $     */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -637,6 +637,8 @@
 #define        PCI_MSI_PENDING         0x14    /* Vector Pending register */
 
 #define        PCI_MSI_CTL_MASK        __BITS(31, 16)
+#define        PCI_MSI_CTL_EXTMDATA_EN __SHIFTIN(__BIT(10), PCI_MSI_CTL_MASK)
+#define        PCI_MSI_CTL_EXTMDATA_CAP __SHIFTIN(__BIT(9), PCI_MSI_CTL_MASK)
 #define        PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK)
 #define        PCI_MSI_CTL_64BIT_ADDR  __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK)
 #define        PCI_MSI_CTL_MME_MASK    __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK)
@@ -920,6 +922,7 @@
 #define PCIE_DCSR_URD          __BIT(3 + 16)  /* Unsupported Req. Detected */
 #define PCIE_DCSR_AUX_PWR      __BIT(4 + 16)  /* Aux Power Detected */
 #define PCIE_DCSR_TRANSACTION_PND __BIT(5 + 16) /* Transaction Pending */
+#define PCIE_DCSR_EMGPWRREDD   __BIT(6 + 16)  /* Emg. Pwr. Reduct. Detected */
 #define PCIE_LCAP      0x0c    /* Link Capabilities Register */
 #define PCIE_LCAP_MAX_SPEED    __BITS(3, 0)   /* Max Link Speed */
 #define PCIE_LCAP_MAX_WIDTH    __BITS(9, 4)   /* Maximum Link Width */
@@ -1015,6 +1018,8 @@
 #define PCIE_DCAP2_EXTFMT_FLD  __BIT(20)      /* Extended Fmt Field Support */
 #define PCIE_DCAP2_EETLP_PREF  __BIT(21)      /* End-End TLP Prefix Support */
 #define PCIE_DCAP2_MAX_EETLP   __BITS(23, 22) /* Max End-End TLP Prefix Sup */
+#define PCIE_DCAP2_EMGPWRRED   __BITS(25, 24) /* Emergency Power Reduc. Sup */
+#define PCIE_DCAP2_EMGPWRRED_INI __BIT(26)     /* Emrg. Pwr. Reduc. Ini. Req */
 #define PCIE_DCAP2_FRS         __BIT(31)      /* FRS Supported */
 #define PCIE_DCSR2     0x28    /* Device Control & Status 2 Register */
 #define PCIE_DCSR2_COMPT_VAL   __BITS(3, 0)   /* Completion Timeout Value */
@@ -1025,7 +1030,8 @@
 #define PCIE_DCSR2_IDO_REQ     __BIT(8)       /* IDO Request Enable */
 #define PCIE_DCSR2_IDO_COMP    __BIT(9)       /* IDO Completion Enable */
 #define PCIE_DCSR2_LTR_MEC     __BIT(10)      /* LTR Mechanism Enable */
-#define PCIE_DCSR2_OBFF_EN     __BITS(14, 13) /* OBPF Enable */
+#define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11)     /* Emergency Power Reduc. Req */
+#define PCIE_DCSR2_OBFF_EN     __BITS(14, 13) /* OBFF Enable */
 #define PCIE_DCSR2_EETLP       __BIT(15)      /* End-End TLP Prefix Blcking */
 #define PCIE_LCAP2     0x2c    /* Link Capabilities 2 Register */
 #define PCIE_LCAP2_SUP_LNKSV   __BITS(7, 1)   /* Supported Link Speeds Vect */