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[src/trunk]: src/sys/arch/arm Use armreg_*_{read, write} instead of handcrafte...
details: https://anonhg.NetBSD.org/src/rev/b5342d1791c0
branches: trunk
changeset: 339181:b5342d1791c0
user: skrll <skrll%NetBSD.org@localhost>
date: Thu Jul 02 08:33:31 2015 +0000
description:
Use armreg_*_{read,write} instead of handcrafted asm
No functional change.
diffstat:
sys/arch/arm/arm/cpufunc.c | 30 +++++++++++++-----------------
sys/arch/arm/arm32/sys_machdep.c | 7 ++++---
2 files changed, 17 insertions(+), 20 deletions(-)
diffs (125 lines):
diff -r 94504b14fb8a -r b5342d1791c0 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Thu Jul 02 05:11:50 2015 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Thu Jul 02 08:33:31 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.155 2015/06/03 02:30:11 hsuenaga Exp $ */
+/* $NetBSD: cpufunc.c,v 1.156 2015/07/02 08:33:31 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.155 2015/06/03 02:30:11 hsuenaga Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.156 2015/07/02 08:33:31 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -1494,17 +1494,16 @@
static inline u_int
get_cachesize_cp15(int cssr)
{
- u_int csid;
-
#if defined(CPU_ARMV7)
__asm volatile(".arch\tarmv7a");
- __asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (cssr));
- __asm volatile("isb" ::: "memory"); /* sync to the new cssr */
+
+ armreg_csselr_write(cssr);
+ arm_isb(); /* sync to the new cssr */
+
#else
__asm volatile("mcr p15, 1, %0, c0, c0, 2" :: "r" (cssr) : "memory");
#endif
- __asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (csid));
- return csid;
+ return armreg_ccsidr_read();
}
#endif
@@ -1565,8 +1564,7 @@
u_int ctype, isize, dsize;
u_int multiplier;
- __asm volatile("mrc p15, 0, %0, c0, c0, 1"
- : "=r" (ctype));
+ ctype = armreg_ctr_read();
/*
* ...and thus spake the ARM ARM:
@@ -3002,7 +3000,7 @@
__asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
/* Allow detection code to find the VFP if it's fitted. */
- __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
+ armreg_cpacr_write(0x0fffffff);
/* Set the control register */
curcpu()->ci_ctrl = cpuctrl;
@@ -3051,7 +3049,7 @@
__asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
/* Allow detection code to find the VFP if it's fitted. */
- __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
+ armreg_cpacr_write(0x0fffffff);
/* Set the control register */
curcpu()->ci_ctrl = cpu_control(cpuctrlmask, cpuctrl);
@@ -3274,7 +3272,7 @@
__asm volatile ("mcr\tp15, 0, %0, c7, c7, 0" : : "r"(sbz));
/* Allow detection code to find the VFP if it's fitted. */
- __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
+ armreg_cpacr_write(0x0fffffff);
/* Set the control register */
curcpu()->ci_ctrl = cpuctrl;
@@ -3592,15 +3590,13 @@
cpu_control(0xffffffff, cpuctrl);
/* Make sure write coalescing is turned on */
- __asm volatile("mrc p15, 0, %0, c1, c0, 1"
- : "=r" (auxctl));
+ auxctl = armreg_auxctl_read();
#ifdef XSCALE_NO_COALESCE_WRITES
auxctl |= XSCALE_AUXCTL_K;
#else
auxctl &= ~XSCALE_AUXCTL_K;
#endif
- __asm volatile("mcr p15, 0, %0, c1, c0, 1"
- : : "r" (auxctl));
+ armreg_auxctl_write(auxctl);
}
#endif /* CPU_XSCALE */
diff -r 94504b14fb8a -r b5342d1791c0 sys/arch/arm/arm32/sys_machdep.c
--- a/sys/arch/arm/arm32/sys_machdep.c Thu Jul 02 05:11:50 2015 +0000
+++ b/sys/arch/arm/arm32/sys_machdep.c Thu Jul 02 08:33:31 2015 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sys_machdep.c,v 1.21 2015/03/22 21:45:12 joerg Exp $ */
+/* $NetBSD: sys_machdep.c,v 1.22 2015/07/02 08:33:31 skrll Exp $ */
/*
* Copyright (c) 1995-1997 Mark Brinicombe.
@@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sys_machdep.c,v 1.21 2015/03/22 21:45:12 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sys_machdep.c,v 1.22 2015/07/02 08:33:31 skrll Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -170,8 +170,9 @@
{
#ifdef _ARM_ARCH_6
if (l == curlwp) {
+ u_int val = (u_int)addr;
kpreempt_disable();
- __asm __volatile("mcr p15, 0, %0, c13, c0, 3" : : "r" (addr));
+ armreg_tpidruro_write(val);
kpreempt_enable();
}
return 0;
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