[src/trunk]: src/sys/arch/aarch64/include Trailing whitespace

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9392f919ff03
branches:  trunk
changeset: 358299:9392f919ff03
user:      skrll <skrll%NetBSD.org@localhost>
date:      Wed Dec 20 14:58:08 2017 +0000

description:
Trailing whitespace

diffstat:

 sys/arch/aarch64/include/armreg.h |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (36 lines):

diff -r cd8cf476cf1c -r 9392f919ff03 sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Wed Dec 20 14:51:40 2017 +0000
+++ b/sys/arch/aarch64/include/armreg.h Wed Dec 20 14:58:08 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.2 2015/04/27 06:54:12 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.3 2017/12/20 14:58:08 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -133,7 +133,7 @@
 AARCH64REG_WRITE_INLINE(nzcv)
 
 static const uintmax_t
-    NZCV_N = __BIT(31), // Negative 
+    NZCV_N = __BIT(31), // Negative
     NZCV_Z = __BIT(30), // Zero
     NZCV_C = __BIT(29), // Carry
     NZCV_V = __BIT(28); // Overflow
@@ -141,7 +141,7 @@
 AARCH64REG_READ_INLINE(tpidr_el0)      // Thread Pointer ID Register (RW)
 AARCH64REG_WRITE_INLINE(tpidr_el0)
 
-/* 
+/*
  * From here on, these can only be accessed at EL1 (kernel)
  */
 
@@ -290,7 +290,7 @@
 
 static const uintmax_t
     SPSR_NZCV    = __BITS(31,28),      // mask of N Z C V
-     SPSR_N      = __BIT(31),          // Negative 
+     SPSR_N      = __BIT(31),          // Negative
      SPSR_Z      = __BIT(30),          // Zero
      SPSR_C      = __BIT(29),          // Carry
      SPSR_V      = __BIT(28),          // oVerflow