[src/trunk]: src/sys/arch/evbarm/exynos Use arm_fdt_cpu_hatch and add mmu ent...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b84c3a3d5e5f
branches:  trunk
changeset: 354292:b84c3a3d5e5f
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Jun 10 23:20:56 2017 +0000

description:
Use arm_fdt_cpu_hatch and add mmu entry for DTB

diffstat:

 sys/arch/evbarm/exynos/exynos_start.S |  23 ++++++++++++++++++++---
 1 files changed, 20 insertions(+), 3 deletions(-)

diffs (58 lines):

diff -r 87c094d8f577 -r b84c3a3d5e5f sys/arch/evbarm/exynos/exynos_start.S
--- a/sys/arch/evbarm/exynos/exynos_start.S     Sat Jun 10 15:13:18 2017 +0000
+++ b/sys/arch/evbarm/exynos/exynos_start.S     Sat Jun 10 23:20:56 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: exynos_start.S,v 1.3 2015/12/17 08:03:06 skrll Exp $   */
+/*     $NetBSD: exynos_start.S,v 1.4 2017/06/10 23:20:56 jmcneill Exp $        */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -45,7 +45,7 @@
 
 #include <evbarm/exynos/platform.h>
 
-RCSID("$NetBSD: exynos_start.S,v 1.3 2015/12/17 08:03:06 skrll Exp $")
+RCSID("$NetBSD: exynos_start.S,v 1.4 2017/06/10 23:20:56 jmcneill Exp $")
 
 
 #if defined(VERBOSE_INIT_ARM)
@@ -68,7 +68,7 @@
 
 #define        TEMP_L1_TABLE   (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
 
-#define        MD_CPU_HATCH    _C_LABEL(gtmr_init_cpu_clock)
+#define        MD_CPU_HATCH    _C_LABEL(arm_fdt_cpu_hatch)
 
 /*
  * Kernel start routine for Exynos 5422 boards running on uboot firmware
@@ -100,6 +100,18 @@
 #endif
        stmia   r4, {r0-r3}                     // Save the arguments
 
+       /* Add DTB PA (1MB) from r2 to MMU init table */
+       movw    r3, #:lower16:(L1_S_SIZE - 1)           /* align DTB PA to 1M */
+       movt    r3, #:upper16:(L1_S_SIZE - 1)
+       bic     r0, r2, r3
+       orr     r0, r0, #1                              /* 1MB mapping */
+       bic     r1, r2, r3
+       movw    r3, #:lower16:(L1_S_PROTO_armv7|L1_S_APv7_KRW|L1_S_CACHEABLE)
+       movt    r3, #:upper16:(L1_S_PROTO_armv7|L1_S_APv7_KRW|L1_S_CACHEABLE)
+       orr     r1, r1, r3
+       adrl    r3, .Lmmu_init_table_dtb                /* table entry addr */
+       stmia   r3, {r0-r1}                             /* patch table entry */
+
        /*
         * For easy and early SoC / PoP dependency, retrieve the IDs
         */
@@ -268,6 +280,11 @@
                EXYNOS_CORE_SIZE / L1_S_SIZE,
                L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
 
+       /* Map DTB location in SDRAM, patched in later */
+.Lmmu_init_table_dtb:
+       MMU_INIT(0, 0, 0, 0)
+
+
        /* end of table */
        MMU_INIT(0, 0, 0, 0)