[src/trunk]: src/sys/arch/x86/include Add the AMD 10h family PMC values. Some...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c5421313ab4c
branches:  trunk
changeset: 351581:c5421313ab4c
user:      maxv <maxv%NetBSD.org@localhost>
date:      Sat Feb 18 16:15:51 2017 +0000

description:
Add the AMD 10h family PMC values. Some values depend on the CPU revision,
they are commented out. Several other values are common with K7, we could
merge them later.

This family of CPUs has a 12bit event selector, contrary to K7 (8bit). The
thing is, i386's PMC interface takes as argument a uint8_t from userland,
so these counters are not accessible (yet).

diffstat:

 sys/arch/x86/include/specialreg.h |  165 +++++++++++++++++++++++++++++++++++++-
 1 files changed, 163 insertions(+), 2 deletions(-)

diffs (183 lines):

diff -r 793894c0befa -r c5421313ab4c sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Sat Feb 18 15:56:03 2017 +0000
+++ b/sys/arch/x86/include/specialreg.h Sat Feb 18 16:15:51 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.93 2017/02/11 15:11:45 maxv Exp $     */
+/*     $NetBSD: specialreg.h,v 1.94 2017/02/18 16:15:51 maxv Exp $     */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -997,7 +997,7 @@
 #define PMC6_RET_SEG_RENAMES           0xd6    /* P-II and P-III only */
 
 /*
- * AMD K7 Event Selector MSR format.
+ * AMD K7 Event Selector MSR format. [Doc: 22007K.pdf, Feb 2002]
  */
 
 #define K7_EVTSEL_EVENT                        0x000000ff
@@ -1084,3 +1084,164 @@
 #define K7_BP1_MATCH                   0xdd
 #define K7_BP2_MATCH                   0xde
 #define K7_BP3_MATCH                   0xdf
+
+/*
+ * AMD 10h family PMCs. [Doc: 31116.pdf, Jan 2013]
+ */
+/*     Register MSRs                   */
+#define MSR_F10H_EVNTSEL0                      0xc0010000
+#define MSR_F10H_EVNTSEL1                      0xc0010001
+#define MSR_F10H_EVNTSEL2                      0xc0010002
+#define MSR_F10H_EVNTSEL3                      0xc0010003
+#define MSR_F10H_PERFCTR0                      0xc0010004
+#define MSR_F10H_PERFCTR1                      0xc0010005
+#define MSR_F10H_PERFCTR2                      0xc0010006
+#define MSR_F10H_PERFCTR3                      0xc0010007
+/*     Event Selector MSR format       */
+#define F10H_EVTSEL_EVENT_MASK                 0x000F000000FF
+#define F10H_EVTSEL_EVENT_SHIFT_LOW            0
+#define F10H_EVTSEL_EVENT_SHIFT_HIGH           32
+#define F10H_EVTSEL_UNIT_MASK                  0x0000FF00
+#define F10H_EVTSEL_UNIT_SHIFT                 8
+#define F10H_EVTSEL_USR                                __BIT(16)
+#define F10H_EVTSEL_OS                         __BIT(17)
+#define F10H_EVTSEL_EDGE                       __BIT(18)
+#define F10H_EVTSEL_RSVD1                      __BIT(19)
+#define F10H_EVTSEL_INT                                __BIT(20)
+#define F10H_EVTSEL_RSVD2                      __BIT(21)
+#define F10H_EVTSEL_EN                         __BIT(22)
+#define F10H_EVTSEL_INV                                __BIT(23)
+#define F10H_EVTSEL_COUNTER_MASK               0xFF000000
+#define F10H_EVTSEL_COUNTER_MASK_SHIFT         24
+/*     Floating Point Events           */
+#define F10H_FP_DISPATCHED_FPU_OPS             0x00
+#define F10H_FP_CYCLES_EMPTY_FPU_OPS           0x01
+#define F10H_FP_DISPATCHED_FASTFLAG_OPS                0x02
+#define F10H_FP_RETIRED_SSE_OPS                        0x03
+#define F10H_FP_RETIRED_MOVE_OPS               0x04
+#define F10H_FP_RETIRED_SERIALIZING_OPS                0x05
+#define F10H_FP_CYCLES_SERIALIZING_OP_SCHEDULER        0x06
+/*     Load/Store and TLB Events       */
+#define F10H_SEGMENT_REG_LOADS                 0x20
+#define        F10H_PIPELINE_RESTART_SELFMOD_CODE      0x21
+#define F10H_PIPELINE_RESTART_PROBE_HIT                0x22
+#define F10H_LS_BUFFER_2_FILL                  0x23
+#define F10H_LOCKED_OPERATIONS                 0x24
+#define F10H_RETIRED_CLFLUSH_INSTRUCTIONS      0x26
+#define F10H_RETIRED_CPUID_INSTRUCTIONS                0x27
+#define F10H_CANCELLED_STORE_LOAD_FORWARD_OPS  0x2A
+#define F10H_SMI_RECEIVED                      0x2B
+/*     Data Cache Events               */
+#define F10H_DATA_CACHE_ACCESSES               0x40
+#define F10H_DATA_CACHE_MISSES                 0x41
+#define F10H_DATA_CACHE_REFILLS_FROM_L2                0x42
+#define F10H_DATA_CACHE_REFILLS_FROM_NORTHBRIDGE       0x43
+#define F10H_CACHE_LINES_EVICTED               0x44
+#define F10H_L1_DTLB_MISS                      0x45
+#define F10H_L2_DTLB_MISS                      0x46
+#define F10H_MISALIGNED_ACCESSES               0x47
+#define F10H_MICROARCH_LATE_CANCEL_OF_ACCESS   0x48
+#define F10H_MICROARCH_EARLY_CANCEL_OF_ACCESS  0x49
+#define F10H_SINGLE_BIT_ECC_ERRORS_RECORDED    0x4A
+#define F10H_PREFETCH_INSTRUCTIONS_DISPATCHED  0x4B
+#define F10H_DCACHE_MISSES_LOCKED_INSTRUCTIONS 0x4C
+#define F10H_L1_DTLB_HIT                       0x4D
+#define F10H_INEFFECTIVE_SOFTWARE_PREFETCHS    0x52
+#define F10H_GLOBAL_TLB_FLUSHES                        0x54
+#define F10H_MEMORY_REQUESTS_BY_TYPE           0x65
+#define F10H_DATA_PREFETCHER                   0x67
+#define F10H_MAB_REQUESTS                      0x68
+#define F10H_MAB_WAIT_CYCLES                   0x69
+#define F10H_NORTHBRIDGE_READ_RESP_BY_COH_STATE        0x6C
+#define F10H_OCTWORDS_WRITTEN_TO_SYSTEM                0x6D
+#define F10H_CPU_CLOCKS_NOT_HALTED             0x76
+#define F10H_REQUESTS_TO_L2_CACHE              0x7D
+#define F10H_L2_CACHE_MISSES                   0x7E
+#define F10H_L2_FILL                           0x7F
+/* F10H_PAGE_SIZE_MISMATCHES (0x01C0): reserved on some revisions */
+/*     Instruction Cache Events        */
+#define F10H_INSTRUCTION_CACHE_FETCHES         0x80
+#define F10H_INSTRUCTION_CACHE_MISSES          0x81
+#define F10H_INSTRUCTION_CACHE_REFILLS_FROM_L2 0x82
+#define F10H_INSTRUCTION_CACHE_REFILLS_FROM_SYS        0x83
+#define F10H_L1_ITLB_MISS                      0x84
+#define F10H_L2_ITLB_MISS                      0x85
+#define F10H_PIPELINE_RESTART_INSTR_STREAM_PROBE       0x86
+#define F10H_INSTRUCTION_FETCH_STALL           0x87
+#define F10H_RETURN_STACK_HITS                 0x88
+#define F10H_RETURN_STACK_OVERFLOWS            0x89
+#define F10H_INSTRUCTION_CACHE_VICTIMS         0x8B
+#define F10H_INSTRUCTION_CACHE_LINES_INVALIDATED       0x8C
+#define F10H_ITLD_RELOADS                      0x99
+#define F10H_ITLD_RELOADS_ABORTED              0x9A
+/*     Execution Unit Events           */
+#define F10H_RETIRED_INSTRUCTIONS              0xC0
+#define F10H_RETIRED_UOPS                      0xC1
+#define F10H_RETIRED_BRANCH_INSTRUCTIONS       0xC2
+#define F10H_RETIRED_MISPREDICTED_BRANCH_INSTR 0xC3
+#define F10H_RETIRED_TAKEN_BRANCH_INSTRUCTIONS 0xC4
+#define F10H_RETIRED_TAKEN_BRANCH_INSTR_MISPREDICTED   0xC5
+#define F10H_RETIRED_FAR_CONTROL_TRANSFERS     0xC6
+#define F10H_RETIRED_BRANCH_RESYNCS            0xC7
+#define F10H_RETIRED_NEAR_RETURNS              0xC8
+#define F10H_RETIRED_NEAR_RETURNS_MISPREDICTED 0xC9
+#define F10H_RETIRED_INDIRECT_BRANCHES_MISPREDICTED    0xCA
+#define F10H_RETIRED_MMX_FP_INSTRUCTIONS       0xCB
+#define F10H_RETIRED_FASTPATH_DOUBLE_OP_INSTR  0xCC
+#define F10H_INTERRUPTS_MASKED_CYCLES          0xCD
+#define F10H_INTERRUPTS_MASKED_CYCLES_INTERRUPT_PENDING        0xCE
+#define F10H_INTERRUPTS_TAKEN                  0xCF
+#define F10H_DECODER_EMPTY                     0xD0
+#define F10H_DISPATCH_STALLS                   0xD1
+#define F10H_DISPATCH_STALLS_BRANCH_ABORT_RETIRE       0xD2
+#define F10H_DISPATCH_STALLS_SERIALIZATION     0xD3
+#define F10H_DISPATCH_STALLS_SEGMENT_LOAD      0xD4
+#define F10H_DISPATCH_STALLS_REORDER_BUF_FULL  0xD5
+#define F10H_DISPATCH_STALLS_RSV_STATION_FULL  0xD6
+#define F10H_DISPATCH_STALLS_FPU_FULL          0xD7
+#define F10H_DISPATCH_STALLS_LS_FULL           0xD8
+#define F10H_DISPATCH_STALLS_WAITING_ALL_QUITE 0xD9
+#define F10H_DISPATCH_STALLS_FAR_TRANSFER      0xDA
+#define F10H_FPU_EXCEPTIONS                    0xDB
+#define F10H_DR0_BREAKPOINT_MATCHES            0xDC
+#define F10H_DR1_BREAKPOINT_MATCHES            0xDD
+#define F10H_DR2_BREAKPOINT_MATCHES            0xDE
+#define F10H_DR3_BREAKPOINT_MATCHES            0xDF
+/* F10H_RETIRED_X87_FP_OPERATIONS (0x01C0): reserved on some revisions */
+/* F10H_IBS_OPS_TAGGED (0x1CF): reserved on some revisions */
+/* F10H_LFENCE_INSTRUCTIONS_RETIRED (0x01D3): reserved on some revisions */
+/* F10H_SFENCE_INSTRUCTIONS_RETIRED (0x01D4): reserved on some revisions */
+/* F10H_MFENCE_INSTRUCTIONS_RETIRED (0x01D5): reserved on some revisions */
+/*     Memory Controller Events        */
+#define F10H_DRAM_ACCESSES                     0xE0
+#define F10H_DRAM_CONTROLLER_PT_OVERFLOWS      0xE1
+#define F10H_MEM_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED  0xE2
+#define F10H_MEM_CONTROLLER_TURNAROUNDS                0xE3
+#define F10H_MEM_CONTROLLER_BYPASS_COUNTER_SATURATION  0xE4
+#define F10H_THERMAL_STATUS                    0xE8
+#define F10H_CPU_IO_REQUESTS_TO_MEMORY_IO      0xE9
+#define F10H_CACHE_BLOCK_COMMANDS              0xEA
+#define F10H_SIZED_COMMANDS                    0xEB
+#define F10H_PROBE_RESPONSES_AND_UPSTREAM_REQUESTS     0xEC
+#define F10H_GART_EVENTS                       0xEE
+#define F10H_MEMORY_CONTROLLER_REQUESTS                0x01F0
+#define F10H_CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE       0x01E0
+#define F10H_IO_TO_DRAM_REQUESTS_TO_TARGET_NODE        0x01E1
+#define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_03       0x01E2
+#define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_03      0x01E3
+#define F10H_CPU_READ_CMD_LATENCY_TARGET_NODE_47       0x01E4
+#define F10H_CPU_READ_CMD_REQUESTS_TARGET_NODE_47      0x01E5
+#define F10H_CPU_CMD_LATENCY_TO_TARGET_NODE_0347       0x01E6
+#define F10H_CPU_REQUESTS_TO_TARGET_NODE_0347  0x01E7
+/*     Link Events                     */
+#define F10H_HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH   0xF6
+#define F10H_HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH   0xF7
+#define F10H_HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH   0xF8
+#define F10H_HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH   0x01F9
+/*     L3 Cache Events                 */
+/* F10H_READ_READ_REQUEST_TO_L3_CACHE (0x04E0): depends on the revision */
+/* F10H_L3_CACHE_MISSES (0x04E1): depends on the revision */
+/* F10H_L3_FILLS_FROM_L2_EVICTIONS (0x04E2): depends on the revision */
+#define F10H_L3_EVICTIONS                      0x04E3
+/* F10H_NONCANCELLED_L3_READ_REQUESTS (0x04ED): depends on the revision */
+