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[src/trunk]: src/sys/arch/arm/vfp In the REENABLE case, make sur the fpexc co...
details: https://anonhg.NetBSD.org/src/rev/0e9c39a941b8
branches: trunk
changeset: 356841:0e9c39a941b8
user: bouyer <bouyer%NetBSD.org@localhost>
date: Mon Oct 16 15:08:24 2017 +0000
description:
In the REENABLE case, make sur the fpexc copy in the pcb also has
VFP_FPEXC_EN set. Otherwise we could trap on every context switch even if
the CPU already has the VFP state.
diffstat:
sys/arch/arm/vfp/vfp_init.c | 10 +++++++++-
1 files changed, 9 insertions(+), 1 deletions(-)
diffs (46 lines):
diff -r 4cb37e8790ea -r 0e9c39a941b8 sys/arch/arm/vfp/vfp_init.c
--- a/sys/arch/arm/vfp/vfp_init.c Mon Oct 16 15:03:57 2017 +0000
+++ b/sys/arch/arm/vfp/vfp_init.c Mon Oct 16 15:08:24 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vfp_init.c,v 1.53 2017/05/26 21:17:46 jmcneill Exp $ */
+/* $NetBSD: vfp_init.c,v 1.54 2017/10/16 15:08:24 bouyer Exp $ */
/*
* Copyright (c) 2008 ARM Ltd
@@ -520,14 +520,17 @@
curcpu()->ci_vfp_evs[1].ev_count++;
}
+ KASSERT((armreg_fpexc_read() & VFP_FPEXC_EN) == 0);
/*
* If the VFP is already enabled we must be bouncing an instruction.
*/
if (flags & PCU_REENABLE) {
uint32_t fpexc = armreg_fpexc_read();
armreg_fpexc_write(fpexc | VFP_FPEXC_EN);
+ fregs->vfp_fpexc |= VFP_FPEXC_EN;
return;
}
+ KASSERT((fregs->vfp_fpexc & VFP_FPEXC_EN) == 0);
/*
* Load and Enable the VFP (so that we can write the registers).
@@ -543,6 +546,8 @@
*/
return;
}
+ KASSERT(curcpu()->ci_pcu_curlwp[PCU_FPU] == NULL);
+ KASSERT(l->l_pcu_cpu[PCU_FPU] == NULL);
load_vfpregs(fregs);
armreg_fpscr_write(fregs->vfp_fpscr);
@@ -562,6 +567,9 @@
struct vfpreg * const fregs = &pcb->pcb_vfp;
uint32_t fpexc = armreg_fpexc_read();
+ KASSERT(curcpu()->ci_pcu_curlwp[PCU_FPU] == l);
+ KASSERT(curcpu() == l->l_pcu_cpu[PCU_FPU]);
+ KASSERT(curlwp == l || curlwp->l_pcu_cpu[PCU_FPU] != curcpu());
/*
* Enable the VFP (so we can read the registers).
* Make sure the exception bit is cleared so that we can
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