[src/trunk]: src/sys/dev/pci/ixgbe Improve a comment about reading EICS regis...

[knakahara <knakahara%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6a93056e667f
branches:  trunk
changeset: 359669:6a93056e667f
user:      knakahara <knakahara%NetBSD.org@localhost>
date:      Tue Feb 20 08:49:23 2018 +0000

description:
Improve a comment about reading EICS register defined write-only by spec.

It seems that is workaround for silicon errata.

ok by msaitoh@n.o.

diffstat:

 sys/dev/pci/ixgbe/ixgbe.c |  8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diffs (22 lines):

diff -r 1b73bb6d1415 -r 6a93056e667f sys/dev/pci/ixgbe/ixgbe.c
--- a/sys/dev/pci/ixgbe/ixgbe.c Tue Feb 20 07:30:57 2018 +0000
+++ b/sys/dev/pci/ixgbe/ixgbe.c Tue Feb 20 08:49:23 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ixgbe.c,v 1.124 2018/02/20 07:24:37 msaitoh Exp $ */
+/* $NetBSD: ixgbe.c,v 1.125 2018/02/20 08:49:23 knakahara Exp $ */
 
 /******************************************************************************
 
@@ -2838,6 +2838,12 @@
        IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER);
 
        /* First get the cause */
+       /*
+        * The specifications of 82598, 82599, X540 and X550 say EICS register
+        * is write only. However, Linux says it is a workaround for silicon
+        * errata to read EICS instead of EICR to get interrupt cause. It seems
+        * there is a problem about read clear mechanism for EICR register.
+        */
        eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
        /* Be sure the queue bits are not cleared */
        eicr &= ~IXGBE_EICR_RTX_QUEUE;