[src/trunk]: src/sys/arch/arm/include/arm32 Trailing whitespace

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/57509b915cba
branches:  trunk
changeset: 354573:57509b915cba
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Jun 22 08:44:21 2017 +0000

description:
Trailing whitespace

diffstat:

 sys/arch/arm/include/arm32/frame.h |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (36 lines):

diff -r c2bcb28bb39c -r 57509b915cba sys/arch/arm/include/arm32/frame.h
--- a/sys/arch/arm/include/arm32/frame.h        Thu Jun 22 08:31:54 2017 +0000
+++ b/sys/arch/arm/include/arm32/frame.h        Thu Jun 22 08:44:21 2017 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: frame.h,v 1.42 2015/04/17 17:28:33 matt Exp $  */
+/*     $NetBSD: frame.h,v 1.43 2017/06/22 08:44:21 skrll Exp $ */
 
 /*
  * Copyright (c) 1994-1997 Mark Brinicombe.
@@ -64,7 +64,7 @@
        u_int   sf_sp;
        u_int   sf_pc;
 };
- 
+
 /*
  * System stack frames.
  */
@@ -240,7 +240,7 @@
 #define        ENABLE_ALIGNMENT_FAULTS                                         \
        and     r7, r0, #(PSR_MODE)     /* Test for USR32 mode */       ;\
        GET_CURCPU(r4)                  /* r4 = cpuinfo */
-       
+
 
 #define        DO_AST_AND_RESTORE_ALIGNMENT_FAULTS                             \
        DO_PENDING_SOFTINTS                                             ;\
@@ -423,7 +423,7 @@
  * This should only be used if the processor is not currently in SVC32
  * mode. The processor mode is switched to SVC mode and the trap frame is
  * stored. The SVC lr field is used to store the previous value of
- * lr in SVC mode.  
+ * lr in SVC mode.
  *
  * NOTE: r13 and r14 are stored separately as a work around for the
  * SA110 rev 2 STM^ bug