[src/trunk]: src/sys/arch/x86/include - Add Intel cpuid 7 %edx bit 29 IA32_AR...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/34c9aef21d76
branches:  trunk
changeset: 358728:34c9aef21d76
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Jan 15 06:08:40 2018 +0000

description:
- Add Intel cpuid 7 %edx bit 29 IA32_ARCH_CAPABILITIES supported bit.
- Add comment.

diffstat:

 sys/arch/x86/include/specialreg.h |  7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diffs (31 lines):

diff -r f78370bdb864 -r 34c9aef21d76 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Mon Jan 15 05:04:58 2018 +0000
+++ b/sys/arch/x86/include/specialreg.h Mon Jan 15 06:08:40 2018 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.108 2018/01/13 17:55:57 jdolecek Exp $        */
+/*     $NetBSD: specialreg.h,v 1.109 2018/01/15 06:08:40 msaitoh Exp $ */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -322,6 +322,7 @@
  *     %eax: The Maximum input value for supported subleaf.
  *     %ebx: Feature bits.
  *     %ecx: Feature bits.
+ *     %edx: Feature bits.
  */
 
 /* %ebx */
@@ -396,10 +397,12 @@
 #define CPUID_SEF_AVX512_4FMAPS        __BIT(3)
 #define CPUID_SEF_IBRS         __BIT(26) /* IBRS / IBPB Speculation Control */
 #define CPUID_SEF_STIBP                __BIT(27) /* STIBP Speculation Control */
+#define CPUID_SEF_ARCH_CAP     __BIT(29) /* IA32_ARCH_CAPABILITIES */
 
 #define CPUID_SEF_FLAGS2       "\20" \
                                "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
-                                       "\33" "IBRS"    "\34" "STIBP"
+                                       "\33" "IBRS"    "\34" "STIBP"   \
+                       "\36" "ARCH_CAP"
 
 /*
  * CPUID Processor extended state Enumeration Fn0000000d