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[src/trunk]: src/sys/arch/powerpc/oea deal with ppc970's HID0
details: https://anonhg.NetBSD.org/src/rev/3134c55ab6a3
branches: trunk
changeset: 354998:3134c55ab6a3
user: macallan <macallan%NetBSD.org@localhost>
date: Fri Jul 07 22:30:28 2017 +0000
description:
deal with ppc970's HID0
diffstat:
sys/arch/powerpc/oea/cpu_subr.c | 82 ++++++++++++++++++++++++++++++++++-------
1 files changed, 68 insertions(+), 14 deletions(-)
diffs (162 lines):
diff -r eafdf91837e4 -r 3134c55ab6a3 sys/arch/powerpc/oea/cpu_subr.c
--- a/sys/arch/powerpc/oea/cpu_subr.c Fri Jul 07 22:22:11 2017 +0000
+++ b/sys/arch/powerpc/oea/cpu_subr.c Fri Jul 07 22:30:28 2017 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_subr.c,v 1.82 2014/03/24 19:29:59 christos Exp $ */
+/* $NetBSD: cpu_subr.c,v 1.83 2017/07/07 22:30:28 macallan Exp $ */
/*-
* Copyright (c) 2001 Matt Thomas.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.82 2014/03/24 19:29:59 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.83 2017/07/07 22:30:28 macallan Exp $");
#include "opt_ppcparam.h"
#include "opt_ppccache.h"
@@ -328,6 +328,9 @@
return;
__asm volatile(
+#if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE)
+ "dssall;"
+#endif
"sync;"
"mfmsr %0;"
"oris %0,%0,%1@h;" /* enter power saving mode */
@@ -484,14 +487,25 @@
return (ci);
}
+#define HAVE_64BIT_HID0 (defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64))
+
void
cpu_setup(device_t self, struct cpu_info *ci)
{
- u_int hid0, hid0_save, pvr, vers;
+ u_int pvr, vers;
const char * const xname = device_xname(self);
const char *bitmask;
char hidbuf[128];
char model[80];
+#if HAVE_64BIT_HID0
+ char hidbuf_u[128];
+ const char *bitmasku = NULL;
+#endif
+#if defined(PPC_OEA64_BRIDGE)
+ volatile uint64_t hid0;
+#else
+ register_t hid0;
+#endif
pvr = mfpvr();
vers = (pvr >> 16) & 0xffff;
@@ -503,7 +517,11 @@
/* set the cpu number */
ci->ci_cpuid = cpu_number();
- hid0_save = hid0 = mfspr(SPR_HID0);
+#if defined(_ARCH_PPC64)
+ __asm volatile("mfspr %0,%1" : "=r"(hid0) : "K"(SPR_HID0));
+#else
+ hid0 = mfspr(SPR_HID0);
+#endif
cpu_probe_cache();
@@ -564,6 +582,13 @@
case IBM970:
case IBM970FX:
case IBM970MP:
+#if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE)
+ hid0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP);
+ hid0 |= HID0_64_DOZE | HID0_64_DPM | HID0_64_EX_TBEN |
+ HID0_64_TB_CTRL | HID0_64_EN_MCHK;
+ powersave = 1;
+ break;
+#endif
case IBMPOWER3II:
default:
/* No power-saving mode is available. */ ;
@@ -598,17 +623,31 @@
break;
}
-#ifdef MULTIPROCESSOR
+ /*
+ * according to the 603e manual this is necessary for an external L2
+ * cache to work properly
+ */
switch (vers) {
case MPC603e:
hid0 |= HID0_ABE;
}
+
+#if defined(_ARCH_PPC64)
+ /* ppc970 needs extre goop around writes to HID0 */
+ __asm volatile( "sync;" \
+ "mtspr %0,%1;" \
+ "mfspr %1,%0;" \
+ "mfspr %1,%0;" \
+ "mfspr %1,%0;" \
+ "mfspr %1,%0;" \
+ "mfspr %1,%0;" \
+ "mfspr %1,%0;" \
+ : : "K"(SPR_HID0), "r"(hid0));
+#else
+ mtspr(SPR_HID0, hid0);
#endif
-
- if (hid0 != hid0_save) {
- mtspr(SPR_HID0, hid0);
- __asm volatile("sync;isync");
- }
+ __asm volatile("sync;isync");
+
switch (vers) {
@@ -623,14 +662,30 @@
case IBM970:
case IBM970FX:
case IBM970MP:
- bitmask = 0;
+ bitmask = HID0_970_BITMASK;
+#if HAVE_64BIT_HID0
+ bitmasku = HID0_970_BITMASK_U;
+#endif
break;
default:
bitmask = HID0_BITMASK;
break;
}
- snprintb(hidbuf, sizeof hidbuf, bitmask, hid0);
- aprint_normal_dev(self, "HID0 %s, powersave: %d\n", hidbuf, powersave);
+
+#if HAVE_64BIT_HID0
+ if (bitmasku != NULL) {
+ printf("HID0 %llx\n", hid0);
+ snprintb(hidbuf, sizeof hidbuf, bitmask, hid0 & 0xffffffff);
+ snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid0 >> 32);
+ aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n",
+ hidbuf_u, hidbuf, powersave);
+ } else
+#endif
+ {
+ snprintb(hidbuf, sizeof hidbuf, bitmask, hid0);
+ aprint_normal_dev(self, "HID0 %s, powersave: %d\n",
+ hidbuf, powersave);
+ }
ci->ci_khz = 0;
@@ -1166,7 +1221,6 @@
}
}
-
/* Find the temperature of the CPU. */
void
cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
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